Invention Grant
- Patent Title: Nanowire transistor structure and method of shaping
-
Application No.: US16013329Application Date: 2018-06-20
-
Publication No.: US11869973B2Publication Date: 2024-01-09
- Inventor: Erica J. Thompson , Aditya Kasukurti , Jun Sung Kang , Kai Loon Cheong , Biswajeet Guha , William Hsu , Bruce Beattie
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L29/66 ; H01L21/02 ; H01L21/311 ; H01L29/165 ; H01L29/205 ; H01L29/423
Abstract:
A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
Public/Granted literature
- US20190393350A1 NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING Public/Granted day:2019-12-26
Information query
IPC分类:
