公开(公告)号：US20190393350A1

公开(公告)日：2019-12-26

申请号：US16013329

申请日：2018-06-20

Applicant: INTEL CORPORATION

Inventor： Erica J. Thompson ,  Aditya Kasukurti ,  Jun Sung Kang ,  Kai Loon Cheong ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

公开(公告)号：US20240332379A1

公开(公告)日：2024-10-03

申请号：US18129688

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Shaun Mills ,  Ehren Mannebach ,  Mauro Kobrinsky ,  Kai Loon Cheong ,  Makram Abd El Qader

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775

Abstract: Devices, transistor structures, systems, and techniques are described herein related to backside contacts for field effect transistors formed using a backside contact etch prior to cavity spacer formation. A transistor includes semiconductor structures such as nanoribbons extending between a source and a drain. A spacer material is between a gate and the source/drain as cavity spacer fill. The spacer material is also between a portion of a backside contact and a portion of the source/drain, to eliminate a short between the backside contact and the gate.

公开(公告)号：US20240006499A1

公开(公告)日：2024-01-04

申请号：US17854242

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Kai Loon Cheong ,  Pooja Nath ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Charles C. Kuo ,  Nicole K. Thomas ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Thoe Michaelos ,  David Kohen

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/6681

Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.

公开(公告)号：US20230395678A1

公开(公告)日：2023-12-07

申请号：US17831802

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Munzarin F. Qayyum ,  Nicole K. Thomas ,  Jami A. Wiedemer ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Willy Rachmady ,  Cheng-Ying Huang ,  Rohit Galatage ,  Nitesh Kumar ,  Kai Loon Cheong ,  Venkata Vasiraju

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L27/092

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41733 ,  H01L27/0924

Abstract: A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.

公开(公告)号：US11869973B2

公开(公告)日：2024-01-09

申请号：US16013329

申请日：2018-06-20

Applicant: INTEL CORPORATION

Inventor： Erica J. Thompson ,  Aditya Kasukurti ,  Jun Sung Kang ,  Kai Loon Cheong ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/165 ,  H01L29/205 ,  H01L29/423

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7855 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/31111 ,  H01L21/31122 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

公开(公告)号：US11869891B2

公开(公告)日：2024-01-09

申请号：US16146808

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Jun Sung Kang ,  Kai Loon Cheong ,  Erica J. Thompson ,  Biswajeet Guha ,  William Hsu ,  Dax M. Crum ,  Tahir Ghani ,  Bruce Beattie

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/161 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

公开(公告)号：US20250006737A1

公开(公告)日：2025-01-02

申请号：US18216520

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Aryan Navabi-Shirazi ,  Michael Babb ,  Kai Loon Cheong ,  Cheng-Ying Huang ,  Mohammad Hasan ,  Leonard P. Guler ,  Marko Radosavljevic

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.

公开(公告)号：US20240088296A1

公开(公告)日：2024-03-14

申请号：US18514974

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Erica J. THOMPSON ,  Aditya Kasukurti ,  Jun Sung Kang ,  Kai Loon Cheong ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7855 ,  H01L21/02238

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

公开(公告)号：US20200161440A1

公开(公告)日：2020-05-21

申请号：US16615111

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Ritesh Jhaveri ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao ,  Karthik Jambunathan ,  Scott J. Maddox ,  Kai Loon Cheong ,  Anand S. Murthy

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region comprising doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region comprising doped semiconductor material on the substrate adjacent a second side of the semiconductor region, a substantially conformal semiconductor layer over a surface of a recess in the source region, and a metal over the conformal layer substantially filling the recess in the source region. Other embodiments are also disclosed and claimed.