Invention Grant
- Patent Title: Mechanism of enabling fault handling with PCIE re-timer
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Application No.: US17255317Application Date: 2018-09-28
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Publication No.: US11874724B2Publication Date: 2024-01-16
- Inventor: Haifeng Gong , Manisha M. Nilange , Shiwei Xu , Xiaoxia Fu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- International Application: PCT/CN2018/108442 2018.09.28
- International Announcement: WO2020/062075A 2020.04.02
- Date entered country: 2020-12-22
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07 ; G06F13/40 ; G06F13/42

Abstract:
An extension device is positioned within a point-to-point link to connect two devices, where the extension device includes error detection circuitry to detect a set of errors at the extension device. The extension device further includes memory to store an event register, where the extension device is to write data to the event register to describe detection of an error by the error detection circuitry. The extension device further includes a transmitter to transmit a notification signal to indicate the detection of the error and presence of data in the evert register associated with the error.
Public/Granted literature
- US20210271537A1 A MECHANISM OF ENABLING FAULT HANDLING WITH PCIE RE-TIMER Public/Granted day:2021-09-02
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