Invention Grant
- Patent Title: Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture
-
Application No.: US17724769Application Date: 2022-04-20
-
Publication No.: US11894072B2Publication Date: 2024-02-06
- Inventor: Jiacen Guo , Xiang Yang , Abhijith Prakash
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: Dickinson Wright PLLC
- Main IPC: G11C16/08
- IPC: G11C16/08 ; G11C16/34 ; G11C11/56 ; G11C16/10 ; G11C16/04

Abstract:
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.
Public/Granted literature
- US20230343400A1 TWO-SIDE STAIRCASE PRE-CHARGE IN SUB-BLOCK MODE OF THREE-TIER NON-VOLATILE MEMORY ARCHITECTURE Public/Granted day:2023-10-26
Information query