Invention Grant
- Patent Title: Transistor isolation regions and methods of forming the same
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Application No.: US17385561Application Date: 2021-07-26
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Publication No.: US11908751B2Publication Date: 2024-02-20
- Inventor: Szu-Ying Chen , Sen-Hong Syue , Huicheng Chang , Yee-Chia Yeo
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L21/762 ; H01L21/02

Abstract:
In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.
Public/Granted literature
- US20220359311A1 Transistor Isolation Regions and Methods of Forming the Same Public/Granted day:2022-11-10
Information query
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