公开(公告)号：US20250079162A1

公开(公告)日：2025-03-06

申请号：US18952021

申请日：2024-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US20240274606A1

公开(公告)日：2024-08-15

申请号：US18646277

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the fist insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

公开(公告)号：US11978758B2

公开(公告)日：2024-05-07

申请号：US17166387

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Pao-Tung Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

IPC: H01L27/14 ,  H01L21/768 ,  H01L23/498 ,  H01L27/146 ,  H01L23/538

CPC classification number: H01L27/14687 ,  H01L21/76898 ,  H01L23/49827 ,  H01L27/14636 ,  H01L27/1469 ,  H01L21/76831 ,  H01L23/5384 ,  H01L27/14634 ,  H01L27/1464 ,  H01L2223/6622 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.

公开(公告)号：US11587910B2

公开(公告)日：2023-02-21

申请号：US17223292

申请日：2021-04-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Meng-Hsun Wan ,  Dun-Nian Yaung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

公开(公告)号：US20220208749A1

公开(公告)日：2022-06-30

申请号：US17696565

申请日：2022-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Ting Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Szu-Ying Chen ,  U-Ting Chen

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.

公开(公告)号：US20210159264A1

公开(公告)日：2021-05-27

申请号：US17166387

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Pao-Tung Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

IPC: H01L27/146 ,  H01L23/498 ,  H01L21/768

Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.

公开(公告)号：US12183573B2

公开(公告)日：2024-12-31

申请号：US18365517

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US12068287B2

公开(公告)日：2024-08-20

申请号：US18170790

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Meng-Hsun Wan ,  Dun-Nian Yaung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/03019 ,  H01L2224/033 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0384 ,  H01L2224/03848 ,  H01L2224/04105 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/08058 ,  H01L2224/08145 ,  H01L2224/80357 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/9202 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/80986 ,  H01L2224/80895 ,  H01L2224/8083 ,  H01L2224/9202 ,  H01L2224/03 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/00014

Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

公开(公告)号：US20240266341A1

公开(公告)日：2024-08-08

申请号：US18640167

申请日：2024-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/06515 ,  H01L2224/08052 ,  H01L2224/08146 ,  H01L2224/0913 ,  H01L2224/09515 ,  H01L2224/09517 ,  H01L2224/48463 ,  H01L2224/8122 ,  H01L2224/81359 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437

Abstract: A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

公开(公告)号：US11996412B2

公开(公告)日：2024-05-28

申请号：US17818598

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/94 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78 ,  H01L31/113

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.