公开(公告)号：US20240379461A1

公开(公告)日：2024-11-14

申请号：US18784355

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092

Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

公开(公告)号：US12040382B2

公开(公告)日：2024-07-16

申请号：US17322405

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chi Yu ,  Cheng-I Chu ,  Chen-Fong Tsai ,  Yi-Rui Chen ,  Sen-Hong Syue ,  Wen-Kai Lin ,  Yoh-Rong Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/02236 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

公开(公告)号：US11923235B2

公开(公告)日：2024-03-05

申请号：US17877824

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

CPC classification number: H01L21/76229 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/785 ,  H01L27/105 ,  H01L27/1463

Abstract: A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.

公开(公告)号：US11901218B2

公开(公告)日：2024-02-13

申请号：US17715261

申请日：2022-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US11854800B2

公开(公告)日：2023-12-26

申请号：US17329477

申请日：2021-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Ya-Wen Chiu ,  Cheng-Po Chau ,  Yi Che Chan ,  Chih Ping Liao ,  YungHao Wang ,  Sen-Hong Syue

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L21/02321 ,  H01L21/02271 ,  H01L21/02345 ,  H01L21/02373 ,  H01L21/76224 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

公开(公告)号：US20220278097A1

公开(公告)日：2022-09-01

申请号：US17186293

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

公开(公告)号：US20220262925A1

公开(公告)日：2022-08-18

申请号：US17322405

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chi Yu ,  Cheng-I Chu ,  Chen-Fong Tsai ,  Yi-Rui Chen ,  Sen-Hong Syue ,  Wen-Kai Lin ,  Yoh-Rong Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285 ,  H01L21/8238

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

公开(公告)号：US20240274606A1

公开(公告)日：2024-08-15

申请号：US18646277

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the fist insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

公开(公告)号：US20220336636A1

公开(公告)日：2022-10-20

申请号：US17230224

申请日：2021-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yoh-Rong Liu ,  Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Li-Chi Yu ,  Sen-Hong Syue

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

公开(公告)号：US10157770B2

公开(公告)日：2018-12-18

申请号：US15660107

申请日：2017-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/70 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure STI, and semiconductor fins. The first isolation structure is on the substrate and has a first thickness. The second isolation structure abuts the first isolation structure and has a second thickness. The first thickness is different from the second thickness. The semiconductor fins respectively abut the first isolation structure and the second isolation structure.