- 专利标题: Layout designs of integrated circuits having backside routing tracks
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申请号: US17833531申请日: 2022-06-06
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公开(公告)号: US11908852B2公开(公告)日: 2024-02-20
- 发明人: Wei-An Lai , Shih-Wei Peng , Wei-Cheng Lin , Jiann-Tyng Tzeng
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- 当前专利权人地址: TW Hsinchu
- 代理机构: Hauptman Ham, LLP
- 主分类号: H01L27/02
- IPC分类号: H01L27/02 ; H01L21/8238 ; H01L23/522 ; H03K19/17736
摘要:
An integrated circuit includes a first transistor, a horizontal routing track extending in a first direction in a first metal layer, and a via connector conductively connecting the horizontal routing track to a first terminal of the first transistor. The integrated circuit also includes a backside routing track extending in the first direction in a backside metal layer, and a backside via connector conductively connecting the backside routing track to a second terminal of the first transistor. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. In the integrated circuit, either the first terminal or the second terminal is a gate terminal of the first transistor.
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