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    Integrated circuit and method for forming the same
    4.
    发明授权
    Integrated circuit and method for forming the same 有权

    公开(公告)号：US11637066B2

    公开(公告)日：2023-04-25

    申请号：US17142016

    申请日：2021-01-05

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Shih-Wei Peng ,  Wei-Cheng Lin ,  Cheng-Chi Chuang ,  Jiann-Tyng Tzeng

    IPC分类号： H01L23/528 ,  H01L29/423 ,  H01L29/786 ,  H01L23/522 ,  H01L29/66 ,  H01L21/768

    摘要： An integrated circuit includes a strip structure having a front side and a back side. A gate structure is on the front side of the strip structure. The integrated circuit includes a plurality of channel layers above the front side of the strip structure, wherein each of the plurality of channel layers is enclosed within the gate structure. An isolation structure surrounds the strip structure. The integrated circuit includes a backside via in the isolation structure. An epitaxy structure is on the front side of the strip structure. The integrated circuit includes a contact over the epitaxy structure. The contact has a first portion on a first side of the epitaxy structure. The first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and contacting the backside via.

    Integrated circuit including supervia and method of making
    6.
    发明授权
    Integrated circuit including supervia and method of making 有权

    公开(公告)号：US11270936B2

    公开(公告)日：2022-03-08

    申请号：US16530770

    申请日：2019-08-02

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

    摘要： An integrated circuit includes a substrate and a first conductive line extending in a first direction parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate. The integrated circuit further includes a second conductive line extending in a second direction parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is greater than the first distance. The integrated circuit further includes a third conductive line extending in the first direction, wherein the second conductive line is a third distance from the top surface of the substrate, and the third distance is greater than the second distance. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line.

    LAYOUT ARCHITECTURE FOR A CELL
    9.
    发明申请
    LAYOUT ARCHITECTURE FOR A CELL 有权

    公开(公告)号：US20210202466A1

    公开(公告)日：2021-07-01

    申请号：US16731387

    申请日：2019-12-31

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shi-Wei Peng ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin ,  Guo-Huei Wu

    IPC分类号： H01L27/02 ,  H01L23/522

    摘要： A circuit includes a first metal layer having a first first metal layer strip adjacent to a first boundary and a second first metal layer strip adjacent to a second boundary opposite to the first boundary. The first and second first metal layer strips, the first boundary, and the second boundary are parallel to each other. The circuit further includes a second metal layer having a first second metal layer strip and a second second metal layer strip adjacent to the first second metal layer strip. The first second metal layer strip is connected to the first metal layer strip at the first first metal layer strip and the second second metal layer strip is connected to the first metal layer strip at the second first metal layer strip. Each of the first and the second second metal layer strips are parallel to each other.

    Semiconductor structure, device, and method
    10.
    发明授权
    Semiconductor structure, device, and method 有权

    公开(公告)号：US10977417B2

    公开(公告)日：2021-04-13

    申请号：US16571809

    申请日：2019-09-16

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

    IPC分类号： G06F17/50 ,  G06F30/398 ,  G03F1/70 ,  G03F1/36

    摘要： A structure includes first, second, third, and fourth conductive segments, and a gate. The first and second conductive segments are in a first conductive layer and configured as first and second terminals of a first transistor of a first type. The third and fourth conductive segments are in a second conductive layer stacked over the first conductive layer and configured as first and second terminals of a second transistor of a second type. The first gate is arranged, in a first direction, between the first and third conductive segments and the second and fourth conductive segments. The gate is configured as a control terminal of the first transistor and a control terminal of the second transistor, the first conductive segment is offset from the third conductive segment along the first direction, and the second conductive segment is offset from the fourth conductive segment along the first direction.