公开(公告)号：US12142611B2

公开(公告)日：2024-11-12

申请号：US17075559

申请日：2020-10-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC: H01L27/12 ,  G06F30/392 ,  G06F119/12

Abstract: A layout method includes: generating a design data including an electronic circuit; and generating a design layout by placing a cell corresponding to the electronic circuit. The cell includes a first transistor and a second transistor over the first transistor. The first transistor includes a gate extending in a first direction, a first active region arranged in a first layer and extending in a second direction, and a first conductive line and a second conductive line arranged on two sides of the first active region. The second transistor includes the gate, a second active region arranged in a second layer over the first layer and extending in the second direction, and a third conductive line and a fourth conductive line arranged on two sides of the second active region. At least one of the four conductive lines includes a first portion non-overlapped with the gate in the first direction.

公开(公告)号：US12068305B2

公开(公告)日：2024-08-20

申请号：US17216420

申请日：2021-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Lin ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Wei-An Lai

IPC: H01L21/70 ,  G06F30/39 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0207 ,  G06F30/39 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/7851

Abstract: A semiconductor device includes a first transistor having a first fin, wherein a base of the first fin is surrounded by a first dielectric material, the first fin having a first fin height measured from the top surface of the first dielectric material to a top surface of the first fin; and a second transistor having a second fin, wherein a base of the second fin is surrounded by a second dielectric material, the second fin having a second fin height measured from a top surface of the second dielectric material to a top surface of the second fin, wherein the first fin height is different from the second fin height.

公开(公告)号：US12067341B2

公开(公告)日：2024-08-20

申请号：US18358223

申请日：2023-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

IPC: G06F7/50 ,  G03F1/36 ,  G03F1/70 ,  G06F30/398 ,  G09G3/3208 ,  H10K59/131 ,  H10K59/35 ,  H01L27/118 ,  H01L27/12

CPC classification number: G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G09G3/3208 ,  H10K59/131 ,  H10K59/353 ,  H01L2027/11881 ,  H01L27/1248

Abstract: A complementary field effect transistor (CFET) structure includes a vertical stack of first and second transistors, wherein the first transistor includes a first channel extending in a first direction from a first source/drain (S/D) region to a second S/D region through a gate extending in a second direction perpendicular to the first direction and the second transistor includes a second channel extending in the first direction from a third S/D region to a fourth S/D region through the gate. A first conductive trace extends in the first direction over the gate, a first via extends from the first S/D region to the first conductive trace and is aligned with the third S/D region along the second direction, a second via extends from the fourth S/D region to the first conductive trace, and the first via has a first height greater than a second height of the second via.

公开(公告)号：US11935830B2

公开(公告)日：2024-03-19

申请号：US17446515

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng ,  Jiun-Wei Lu

IPC: H01L23/528 ,  H01L21/38 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/38 ,  H01L21/768

Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

公开(公告)号：US11637066B2

公开(公告)日：2023-04-25

申请号：US17142016

申请日：2021-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Wei-Cheng Lin ,  Cheng-Chi Chuang ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/786 ,  H01L23/522 ,  H01L29/66 ,  H01L21/768

Abstract: An integrated circuit includes a strip structure having a front side and a back side. A gate structure is on the front side of the strip structure. The integrated circuit includes a plurality of channel layers above the front side of the strip structure, wherein each of the plurality of channel layers is enclosed within the gate structure. An isolation structure surrounds the strip structure. The integrated circuit includes a backside via in the isolation structure. An epitaxy structure is on the front side of the strip structure. The integrated circuit includes a contact over the epitaxy structure. The contact has a first portion on a first side of the epitaxy structure. The first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and contacting the backside via.

公开(公告)号：US20230053139A1

公开(公告)日：2023-02-16

申请号：US17581365

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Yu Chen ,  Wei-Cheng Tzeng ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  G06F30/392 ,  G06F30/31

Abstract: A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

公开(公告)号：US11270936B2

公开(公告)日：2022-03-08

申请号：US16530770

申请日：2019-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit includes a substrate and a first conductive line extending in a first direction parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate. The integrated circuit further includes a second conductive line extending in a second direction parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is greater than the first distance. The integrated circuit further includes a third conductive line extending in the first direction, wherein the second conductive line is a third distance from the top surface of the substrate, and the third distance is greater than the second distance. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line.

公开(公告)号：US11232248B2

公开(公告)日：2022-01-25

申请号：US16558214

申请日：2019-09-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin ,  Jay Yang

IPC: G06F7/50 ,  G06F30/392 ,  G06F30/394

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing a size of the candidate pattern thereby revising the layout diagram.

公开(公告)号：US11100273B2

公开(公告)日：2021-08-24

申请号：US16674869

申请日：2019-11-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Shun Li Chen ,  Wei-Cheng Lin

IPC: G06F30/00 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/39 ,  G06F30/394

Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.

公开(公告)号：US20210202466A1

公开(公告)日：2021-07-01

申请号：US16731387

申请日：2019-12-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shi-Wei Peng ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin ,  Guo-Huei Wu

IPC: H01L27/02 ,  H01L23/522

Abstract: A circuit includes a first metal layer having a first first metal layer strip adjacent to a first boundary and a second first metal layer strip adjacent to a second boundary opposite to the first boundary. The first and second first metal layer strips, the first boundary, and the second boundary are parallel to each other. The circuit further includes a second metal layer having a first second metal layer strip and a second second metal layer strip adjacent to the first second metal layer strip. The first second metal layer strip is connected to the first metal layer strip at the first first metal layer strip and the second second metal layer strip is connected to the first metal layer strip at the second first metal layer strip. Each of the first and the second second metal layer strips are parallel to each other.