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公开(公告)号：US12131998B2
公开(公告)日：2024-10-29
申请号：US18298172
申请日：2023-04-10
发明人： Te-Hsin Chiu , Kam-Tou Sio , Shih-Wei Peng , Wei-Cheng Lin , Jiann-Tyng Tzeng
IPC分类号： H01L23/528 , H01L21/8238 , H01L27/092
CPC分类号： H01L23/5286 , H01L21/823871 , H01L27/092
摘要： A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, fabricating a first set of vias in a back-side of the substrate, depositing a first set of conductive structures on the back-side on a first level, depositing a second set of conductive structures on the back-side on a second level thereby forming a set of power rails, fabricating a second set of vias in the back-side, and depositing a third set of conductive structures on the back-side on a third level. The first set of vias is electrically coupled to the set of transistors. The second set of vias is electrically coupled to the first and third set of conductive structures. A first structure of the first set of conductive structures is electrically coupled to a first via of the first set of vias.
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公开(公告)号：US12021021B2
公开(公告)日：2024-06-25
申请号：US17459697
申请日：2021-08-27
发明人： Te-Hsin Chiu , Shih-Wei Peng , Wei-Cheng Lin , Jiann-Tyng Tzeng
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/02
CPC分类号： H01L23/5226 , H01L21/76895 , H01L23/528 , H01L27/0207
摘要： An integrated circuit structure is disclosed, including a gate, a first conductive line and a pair of second conductive lines, and a first feed-through via. The gate is disposed on a front side of the integrated circuit structure and extends in a first direction on a first side of a dielectric layer. The first conductive line and a pair of second conductive lines are disposed on a second side, opposite of the first side, of the dielectric layer and on a back side, opposite of the front side, of the integrated circuit structure. The first conductive line is interposed between the pair of second conductive lines in a layout view. The first feed-through via extends through the dielectric layer in a second direction different from the first direction. The first feed-through via couples the gate to the first conductive line.
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公开(公告)号：US11854786B2
公开(公告)日：2023-12-26
申请号：US17344530
申请日：2021-06-10
发明人： Wei-An Lai , Te-Hsin Chiu , Shih-Wei Peng , Wei-Cheng Lin , Jiann-Tyng Tzeng , Chia-Tien Wu
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522
CPC分类号： H01L23/528 , H01L21/76802 , H01L21/76877 , H01L23/5226
摘要： An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer.
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公开(公告)号：US11715636B2
公开(公告)日：2023-08-01
申请号：US17581791
申请日：2022-01-21
发明人： Shih-Wei Peng , Chia-Tien Wu , Jiann-Tyng Tzeng
IPC分类号： H01L21/02 , H01L21/033 , H01L23/58
CPC分类号： H01L21/02172 , H01L21/0337 , H01L23/585
摘要： A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell, the first cell and the second cell are arranged in a first direction; forming a plurality of first metal strips arranged in a second direction and extending in the first direction on a first plane; forming a first trench over a boundary between the first cell and the second cell, a bottom surface of the first trench is located on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall extending in the first direction; and fort plurality of second metal strips extending in the second direction on a third plane over the second plane and including a first second metal strip and a second second metal strip separated by the separating wall.
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公开(公告)号：US11663389B2
公开(公告)日：2023-05-30
申请号：US17232571
申请日：2021-04-16
发明人： Shih-Wei Peng , Kam-Tou Sio , Jiann-Tyng Tzeng
IPC分类号： G06F30/392 , G06F30/394 , G06F30/396
CPC分类号： G06F30/392 , G06F30/394 , G06F30/396
摘要： Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.
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公开(公告)号：US11646314B2
公开(公告)日：2023-05-09
申请号：US17232293
申请日：2021-04-16
发明人： Te-Hsin Chiu , Shih-Wei Peng , Meng-Hung Shen , Jiann-Tyng Tzeng
CPC分类号： H01L27/0924 , H01L29/0649 , H01L29/66795 , H01L29/7851
摘要： In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess.
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公开(公告)号：US20230064223A1
公开(公告)日：2023-03-02
申请号：US17459697
申请日：2021-08-27
发明人： Te-Hsin Chiu , Shih-Wei Peng , Wei-Cheng Lin , Jiann-Tyng Tzeng
IPC分类号： H01L23/522 , H01L23/528 , H01L27/02 , H01L21/768
摘要： An integrated circuit structure is disclosed, including a gate, a first conductive line and a pair of second conductive lines, and a first feed-through via. The gate is disposed on a front side of the integrated circuit structure and extends in a first direction on a first side of a dielectric layer. The first conductive line and a pair of second conductive lines are disposed on a second side, opposite of the first side, of the dielectric layer and on a back side, opposite of the front side, of the integrated circuit structure. The first conductive line is interposed between the pair of second conductive lines in a layout view. The first feed-through via extends through the dielectric layer in a second direction different from the first direction. The first feed-through via couples the gate to the first conductive line.
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公开(公告)号：US20230008779A1
公开(公告)日：2023-01-12
申请号：US17371321
申请日：2021-07-09
发明人： Shih-Wei Peng , Jiann-Tyng Tzeng , Ken-Hsien Hsieh
IPC分类号： H01L23/528 , H01L27/085 , H01L27/092 , H01L21/768
摘要： A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.
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公开(公告)号：US20220352148A1
公开(公告)日：2022-11-03
申请号：US17245757
申请日：2021-04-30
发明人： Kam-Tou Sio , Jiann-Tyng Tzeng , Shih-Wei Peng
IPC分类号： H01L27/06 , H01L23/522 , H01L23/528 , H01L21/822
摘要： A monolithic three dimensional integrated circuit is provided. The monolithic three dimensional integrated circuit includes a first cell layer having a first cell having a first active component of the monolithic three dimensional integrated circuit. A second layer having a second cell including a second active component. The second cell layer is formed vertically above the first cell layer. The first cell layer having the first active component and the second cell layer having the second active component are formed on a single die. The first cell has a smaller metal pitch than the second cell. A buried via electrically couples the first active component of the first cell of the first cell layer with the second active component of the second cell of the second cell layer.
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公开(公告)号：US11374005B2
公开(公告)日：2022-06-28
申请号：US17075578
申请日：2020-10-20
发明人： Shih-Wei Peng , Te-Hsin Chiu , Wei-Cheng Lin , Jiann-Tyng Tzeng
IPC分类号： H01L21/02 , H01L21/8238 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
摘要： A semiconductor device includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. The first transistor is arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device also includes a first conductive line arranged in a third layer between the first layer and the second layer and extending in the second direction, wherein the first conductive line is configured to electrically connect a first source/drain region of the first active region to a second source/drain region of the second active region.
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