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    MEMORY DEVICE AND LAYOUT, MANUFACTURING METHOD OF THE SAME
    4.
    发明公开
    MEMORY DEVICE AND LAYOUT, MANUFACTURING METHOD OF THE SAME 审中-公开

    公开(公告)号：US20230354572A1

    公开(公告)日：2023-11-02

    申请号：US18340900

    申请日：2023-06-26

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Te-Hsin Chiu ,  Jiann-Tyng Tzeng ,  Shih-Wei Peng ,  Wei-An Lai

    IPC分类号： H10B10/00 ,  H01L27/092 ,  G11C5/02 ,  G11C11/412

    CPC分类号： H10B10/12 ,  H01L27/092 ,  G11C5/025 ,  G11C11/412

    摘要： A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    5.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF 审中-公开

    公开(公告)号：US20230352339A1

    公开(公告)日：2023-11-02

    申请号：US18344565

    申请日：2023-06-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-An Lai ,  Jiann-Tyng Tzeng

    IPC分类号： H01L21/762 ,  H01L21/74 ,  H01L21/66 ,  H01L21/3115

    CPC分类号： H01L21/76243 ,  H01L21/31155 ,  H01L21/743 ,  H01L22/14

    摘要： A method includes doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF 有权

    公开(公告)号：US20220238679A1

    公开(公告)日：2022-07-28

    申请号：US17527857

    申请日：2021-11-16

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-An Lai ,  Jiann-Tyng Tzeng

    IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L23/48

    摘要： A semiconductor device and a method of manufacturing the device are disclosed. In one aspect, the semiconductor device includes a first active region that extends along a first lateral direction and includes a plurality of first epitaxial structures. The semiconductor device also includes an interconnect structure that also extends along the first lateral direction and is disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion that offsets from the first active region along a second lateral direction perpendicular to the first lateral direction.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    7.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF 有权

    公开(公告)号：US20220238371A1

    公开(公告)日：2022-07-28

    申请号：US17533000

    申请日：2021-11-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Te-Hsin Chiu ,  Shih-Wei Peng ,  Wei-An Lai ,  Jiann-Tyng Tzeng

    IPC分类号： H01L21/762 ,  H01L21/66 ,  H01L21/74 ,  H01L21/3115

    摘要： A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

    Multiple fin height integrated circuit
    8.
    发明授权
    Multiple fin height integrated circuit 有权

    公开(公告)号：US10964684B2

    公开(公告)日：2021-03-30

    申请号：US16405898

    申请日：2019-05-07

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Wei-Cheng Lin ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Lipen Yuan ,  Wei-An Lai

    IPC分类号： H01L21/336 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  G06F30/39

    摘要： A method of modifying an integrated circuit includes operations related to identifying at least two fin-containing functional areas of the integrated circuit, generating a performance curve for each fin-containing functional area of the integrated circuit for each fin height of a series of fin heights, and determining whether an inflection point exists for each performance curve. The method further includes operations related to selecting a value of a performance characteristic for each of the fin-containing functional areas, the selected value having a corresponding fin height in each of the fin-containing functional areas, modifying each fin-containing functional area to have the fin height corresponding to the selected value of the performance characteristic; and combining the modified fin-containing functional areas to form a modified integrated circuit.