Invention Grant
- Patent Title: Method for singulating chips with laterally insulated flanks
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Application No.: US16950787Application Date: 2020-11-17
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Publication No.: US11923234B2Publication Date: 2024-03-05
- Inventor: Ludovic Fallourd
- Applicant: STMicroelectronics (Tours) SAS
- Applicant Address: FR Tours
- Assignee: STMicroelectronics (Tours) SAS
- Current Assignee: STMicroelectronics (Tours) SAS
- Current Assignee Address: FR Tours
- Agency: Seed IP Law Group LLP
- Priority: FR 12895 2019.11.19
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/02 ; H01L21/56 ; H01L21/762 ; H01L23/00 ; H01L23/31 ; H01L23/367 ; H01L23/495 ; H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L25/065

Abstract:
The present disclosure relates to a method for manufacturing electronic chips. The method includes forming a plurality of trenches on a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed. The trenches delimit laterally a plurality of chips, and each of the chips includes a single integrated circuit. The method further includes electrically isolating flanks of each of the chips by forming an electrically isolating layer on lateral walls of the trenches.
Public/Granted literature
- US20210151347A1 METHOD FOR MANUFACTURING ELECTRONIC CHIPS Public/Granted day:2021-05-20
Information query
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