公开(公告)号：US11923234B2

公开(公告)日：2024-03-05

申请号：US16950787

申请日：2020-11-17

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/56 ,  H01L21/762 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L21/76224 ,  H01L21/0228 ,  H01L21/56

Abstract: The present disclosure relates to a method for manufacturing electronic chips. The method includes forming a plurality of trenches on a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed. The trenches delimit laterally a plurality of chips, and each of the chips includes a single integrated circuit. The method further includes electrically isolating flanks of each of the chips by forming an electrically isolating layer on lateral walls of the trenches.

公开(公告)号：US10236480B2

公开(公告)日：2019-03-19

申请号：US16031099

申请日：2018-07-10

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01M2/04 ,  H01M2/06 ,  H01M2/20 ,  H01M10/04 ,  H01M2/30 ,  H01M2/10

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

公开(公告)号：US20180331332A1

公开(公告)日：2018-11-15

申请号：US16031099

申请日：2018-07-10

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01M2/06 ,  H01M10/04 ,  H01M2/04 ,  H01M2/30 ,  H01M2/10 ,  H01M2/20

CPC classification number: H01M2/06 ,  H01M2/0404 ,  H01M2/0408 ,  H01M2/1022 ,  H01M2/204 ,  H01M2/30 ,  H01M10/0436 ,  H01M10/044 ,  H01M2220/30

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

公开(公告)号：US10044009B2

公开(公告)日：2018-08-07

申请号：US15260008

申请日：2016-09-08

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01M2/06 ,  H01M10/04 ,  H01M2/10 ,  H01M2/04 ,  H01M2/20 ,  H01M2/30

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

公开(公告)号：US12230602B2

公开(公告)日：2025-02-18

申请号：US17811560

申请日：2022-07-08

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Ludovic Fallourd ,  Christophe Serre

IPC: H01L23/00 ,  H01L21/78

Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

公开(公告)号：US11367913B2

公开(公告)日：2022-06-21

申请号：US16270282

申请日：2019-02-07

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Ludovic Fallourd

IPC: H01M50/116 ,  H01M6/40 ,  H01M10/04 ,  H01M10/0585 ,  H01M50/10 ,  H01M50/124 ,  H01M50/209 ,  H01M10/052

Abstract: The disclosure concerns a battery assembly including two batteries having their active layers facing each other and sharing an encapsulation layer.

公开(公告)号：US20180315965A1

公开(公告)日：2018-11-01

申请号：US16031098

申请日：2018-07-10

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01M2/06 ,  H01M10/04 ,  H01M2/04 ,  H01M2/10 ,  H01M2/30 ,  H01M2/20

CPC classification number: H01M2/06 ,  H01M2/0404 ,  H01M2/0408 ,  H01M2/1022 ,  H01M2/204 ,  H01M2/30 ,  H01M10/0436 ,  H01M10/044 ,  H01M2220/30

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

公开(公告)号：US20180069206A1

公开(公告)日：2018-03-08

申请号：US15260008

申请日：2016-09-08

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01M2/06 ,  H01M10/04 ,  H01M2/10 ,  H01M2/04 ,  H01M2/20 ,  H01M2/30

CPC classification number: H01M2/06 ,  H01M2/0404 ,  H01M2/0408 ,  H01M2/1022 ,  H01M2/204 ,  H01M2/30 ,  H01M10/0436 ,  H01M10/044 ,  H01M2220/30

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.