Invention Grant
- Patent Title: Gate all around I/O engineering
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Application No.: US17888894Application Date: 2022-08-16
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Publication No.: US11923441B2Publication Date: 2024-03-05
- Inventor: Steven C. H. Hung , Benjamin Colombeau , Andy Lo , Byeong Chan Lee , Johanes F. Swenberg , Theresa Kramer Guarini , Malcolm J. Bevan
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Servilla Whitney LLC
- The original application number of the division: US17037941 2020.09.30
- Main IPC: H01L29/66
- IPC: H01L29/66 ; C23C8/02 ; C23C8/16 ; C23C8/80 ; C23C16/455 ; C23C16/56 ; C30B29/06 ; C30B29/52 ; H01L21/02 ; H01L29/423

Abstract:
Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.
Public/Granted literature
- US20220399457A1 Gate All Around I/O Engineering Public/Granted day:2022-12-15
Information query
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