公开(公告)号：US09831091B2

公开(公告)日：2017-11-28

申请号：US15171001

申请日：2016-06-02

Applicant: Applied Materials, Inc.

Inventor： Wei Liu ,  Theresa Kramer Guarini ,  Huy Q. Nguyen ,  Malcolm Bevan ,  Houda Graoui ,  Philip A. Bottini ,  Bernard L. Hwang ,  Lara Hawrylchak ,  Rene George

IPC: H01L21/3105 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/28176 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32477 ,  H01L21/3105 ,  H01L29/517

Abstract: Embodiments described herein generally relate to a method and apparatus for plasma treating a process chamber. A substrate having a gate stack formed thereon may be placed in a process chamber, and hydrogen containing plasma may be used to treat the gate stack in order to cure the defects in the gate stack. As the result of hydrogen containing plasma treatment, the gate stack has lower leakage and improved reliability. To protect the process chamber from Hx+ ions and H* radicals generated by the hydrogen containing plasma, the process chamber may be treated with a plasma without the substrate placed therein and prior to the hydrogen containing plasma treatment. In addition, components of the process chamber that are made of a dielectric material may be coated with a ceramic coating including an yttrium containing oxide in order to protect the components from the plasma.

公开(公告)号：US20210043448A1

公开(公告)日：2021-02-11

申请号：US17081256

申请日：2020-10-27

Applicant: Applied Materials, Inc.

Inventor： Ning Li ,  Mihaela A. Balseanu ,  Li-Qun Xia ,  Dongqing Yang ,  Lala Zhu ,  Malcolm J. Bevan ,  Theresa Kramer Guarini ,  Wenbo Yan

IPC: H01L21/02 ,  H01L21/3105 ,  C23C16/458 ,  C23C16/455 ,  C23C16/04 ,  C23C16/02 ,  C23C16/56

Abstract: Processing platforms having a central transfer station with a robot and an environment having greater than or equal to about 0.1% by weight water vapor, a pre-clean chamber connected to a side of the transfer station and a batch processing chamber connected to a side of the transfer station. The processing platform configured to pre-clean a substrate to remove native oxides from a first surface, form a blocking layer using a alkylsilane and selectively deposit a film. Methods of using the processing platforms and processing a plurality of wafers are also described.

公开(公告)号：US09023700B2

公开(公告)日：2015-05-05

申请号：US14299788

申请日：2014-06-09

Applicant: Applied Materials, Inc.

Inventor： Udayan Ganguly ,  Theresa Kramer Guarini ,  Matthew Scott Rogers ,  Yoshitaka Yokota ,  Johanes S. Swenberg ,  Malcolm J. Bevan

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L21/02247 ,  H01L21/02362 ,  H01L21/28202 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

Abstract: Methods and apparatus for selective one-step nitridation of semiconductor substrates is provided. Nitrogen is selectively incorporated in silicon regions of a semiconductor substrate having silicon regions and silicon oxide regions by use of a selective nitridation process. Nitrogen containing radicals may be directed toward the substrate by forming a nitrogen containing plasma and filtering or removing ions from the plasma, or a thermal nitridation process using selective precursors may be performed. A remote plasma generator may be coupled to a processing chamber, optionally including one or more ion filters, showerheads, and radical distributors, or an in situ plasma may be generated and one or more ion filters or shields disposed in the chamber between the plasma generation zone and the substrate support.

Abstract translation: 提供了半导体衬底选择性一步氮化的方法和装置。 通过使用选择性氮化工艺，在具有硅区域和氧化硅区域的半导体衬底的硅区域中选择性地掺入氮气。 可以通过形成含氮等离子体并且从等离子体中过滤或除去离子而将含氮自由基引导向衬底，或者可以使用选择性前体进行热氮化处理。 远程等离子体发生器可以耦合到处理室，任选地包括一个或多个离子过滤器，淋浴喷头和自由基分配器，或者可以产生原位等离子体，并且一个或多个离子过滤器或屏蔽件设置在等离子体生成 区域和基板支撑。

公开(公告)号：US11927482B2

公开(公告)日：2024-03-12

申请号：US17604814

申请日：2020-03-27

Applicant: Applied Materials, Inc.

Inventor： Kin Pong Lo ,  Lara Hawrylchak ,  Malcolm J. Bevan ,  Theresa Kramer Guarini ,  Wei Liu ,  Bernard L. Hwang

IPC: G01J3/28 ,  G01J3/02 ,  G01J3/10 ,  G01J3/443

CPC classification number: G01J3/10 ,  G01J3/0218 ,  G01J3/443 ,  G01J2003/2879

Abstract: One or more embodiments described herein generally relate to systems and methods for calibrating an optical emission spectrometer (OES) used for processing semiconductor substrates. In embodiments herein, a light fixture is mounted to a plate within a process chamber. A light source is positioned within the light fixture such that it provides an optical path that projects directly at a window through which the OES looks into the process chamber for its reading. When the light source is on, the OES measures the optical intensity of radiation from the light source. To calibrate the OES, the optical intensity of the light source is compared at two separate times when the light source is on. If the optical intensity of radiation at the first time is different than the optical intensity of radiation at the second time, the OES is modified.

公开(公告)号：US11923441B2

公开(公告)日：2024-03-05

申请号：US17888894

申请日：2022-08-16

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/455 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6681 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/45536 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L29/42392 ,  H01L29/6653

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US11145761B2

公开(公告)日：2021-10-12

申请号：US16592362

申请日：2019-10-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US09865735B2

公开(公告)日：2018-01-09

申请号：US15152273

申请日：2016-05-11

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US09177787B2

公开(公告)日：2015-11-03

申请号：US14195273

申请日：2014-03-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Theresa Kramer Guarini ,  Wei Liu

IPC: H01L21/02 ,  C23C16/56

CPC classification number: H01L21/02269 ,  C23C16/56 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/67115 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/68757

Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a first temperature; and exposing the first layer to an RF plasma formed from a process gas comprising ammonia (NH3) to transform the first layer into a nitrogen-containing layer, wherein the plasma has an ion energy of less than about 8 eV.

Abstract translation: 本文提供了形成含氮层的方法和装置。 在一些实施例中，一种方法包括将其上设置有第一层的衬底放置在处理室的衬底支撑件上; 将衬底加热至第一温度; 以及将所述第一层暴露于由包含氨（NH 3）的工艺气体形成的RF等离子体，以将所述第一层转化为含氮层，其中所述等离子体的离子能量小于约8eV。

公开(公告)号：USD1034491S1

公开(公告)日：2024-07-09

申请号：US29744119

申请日：2020-07-27

Applicant: Applied Materials, Inc.

Designer： Kin Pong Lo ,  Vladimir Nagorny ,  Wei Liu ,  Theresa Kramer Guarini ,  Bernard L. Hwang ,  Malcolm J. Bevan ,  Jacob Abraham ,  Swayambhu Prasad Behera

Abstract: FIG. 1 is a front isometric top view of an edge ring.
FIG. 2 is a top plan view thereof.
FIG. 3 is a bottom plan view thereof.
FIG. 4 is a first side view thereof.
FIG. 5 is a second side view thereof.
FIG. 6 is an enlarged partial view of the section 6 shown in FIG. 1.
FIG. 7 is a cross sectional view along line 7-7 of FIG. 2 thereof.
FIG. 8 is an enlarged partial side view thereof.
FIG. 9 is an enlarged partial view of the section 9 shown in FIG. 2.
FIG. 10 is an enlarged partial cross sectional view of the section 10 shown in FIG. 7.
FIG. 11 is another front isometric top view thereof assembled with an overhang ring.
FIG. 12 is another top plan view thereof assembled with the overhang ring.
FIG. 13 is a third side view thereof assembled with the overhang ring; and,
FIG. 14 is an enlarged partial cross sectional view along line 14-14 of FIG. 12 thereof assembled with an overhang ring.
The broken lines appearing in FIGS. 1-14 illustrate portions of the edge ring assembly that form no part of the claimed design. The dot-dot-dash broken lines show boundaries of cross sectional or enlarged views that form no part of the claimed design.

公开(公告)号：US20220399457A1

公开(公告)日：2022-12-15

申请号：US17888894

申请日：2022-08-16

Applicant: Applied Materials, Inc.

Inventor： Steven C.H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/56 ,  C23C16/455

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.