公开(公告)号：US20220254647A1

公开(公告)日：2022-08-11

申请号：US17731486

申请日：2022-04-28

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/06

Abstract: A semiconductor structure may include a source, a drain, a plurality of nanowire channels between the source and the drain, and a bottom insulation layer. The plurality of nanowire channels may each have a width defined by the source and drain. The bottom insulation layer may contact a bottom nanowire channel of the plurality of nanowire channels and may be disposed between the source and drain. The bottom insulation layer may have a width no greater than the width of the bottom nanowire channel.

公开(公告)号：US20210104617A1

公开(公告)日：2021-04-08

申请号：US17037941

申请日：2020-09-30

Applicant: Applied Materials, Inc.

Inventor： Steven C.H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/455 ,  C23C16/56

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US20240379438A1

公开(公告)日：2024-11-14

申请号：US18652947

申请日：2024-05-02

Applicant: Applied Materials, Inc.

Inventor： Veeraraghavan S. Basker ,  Kyoung Ha Kim ,  Byeong Chan Lee

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes combining selective recess of a sacrificial layer and isotropic etching of a silicon layer in order to form a protective cap that will allow the silicon layer of the substrate to be etched without affecting the sacrificial layer.

公开(公告)号：US20240234544A1

公开(公告)日：2024-07-11

申请号：US18538267

申请日：2023-12-13

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Benjamin Colombeau ,  Liu Jiang ,  El Mehdi Bazizi ,  Byeong Chan Lee ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  C23C16/02 ,  C23C16/04 ,  C23C16/32 ,  C23C16/40 ,  C23C16/56 ,  C30B25/04 ,  C30B25/18 ,  C30B29/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66553 ,  C23C16/0227 ,  C23C16/045 ,  C23C16/325 ,  C23C16/401 ,  C23C16/56 ,  C30B25/04 ,  C30B25/186 ,  C30B29/06 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise forming an inner spacer liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. The inner spacer liner comprises a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner may be doped with a dopant (e.g., a p-type dopant or an n-type dopant). One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

公开(公告)号：US20240332388A1

公开(公告)日：2024-10-03

申请号：US18609650

申请日：2024-03-19

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Benjamin Colombeau ,  Nicolas Breil ,  Ashish Pal ,  El Mehdi Bazizi ,  Veeraraghavan S. Basker ,  Balasubramanian Pranatharthiharan ,  Pratik B. Vyas ,  Gregory Costrini

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.

公开(公告)号：US11348803B2

公开(公告)日：2022-05-31

申请号：US16850265

申请日：2020-04-16

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee

IPC: H01L21/84 ,  H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06

Abstract: A method may include forming a plasma of a fluorine-containing precursor and contacting a semiconductor substrate with plasma effluents. The semiconductor substrate may include a layer of a first silicon-containing material having a first germanium content formed over the semiconductor substrate, and alternating layers of a second silicon-containing material and a third silicon-containing material over the layer of the first silicon-containing material. The third silicon-containing material may have a second germanium content. The method may further include laterally recessing the third silicon-containing material relative to the first and second silicon-containing materials. The method may further include depositing a spacer material adjacent to the third silicon-containing material relative to the first and second silicon-containing materials. The method may also include etching the first silicon-containing material relative to the second silicon-containing material and the spacer material.

公开(公告)号：US20240128355A1

公开(公告)日：2024-04-18

申请号：US18378850

申请日：2023-10-11

Applicant: Applied Materials, Inc.

Inventor： Nicolas Breil ,  Byeong Chan Lee

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a source region and a drain region adjacent to a superlattice structure on a substrate. The source region and the drain region comprise a metallic silicide material. In some embodiments, a sacrificial material is first deposited and then removed to form a metallic silicide material in the source and drain region.

公开(公告)号：US11923441B2

公开(公告)日：2024-03-05

申请号：US17888894

申请日：2022-08-16

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/455 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6681 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/45536 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L29/42392 ,  H01L29/6653

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US10927451B2

公开(公告)日：2021-02-23

申请号：US16541688

申请日：2019-08-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Bencherki Mebarki ,  Byeong Chan Lee ,  Huixiong Dai ,  Tejinder Singh ,  Joung Joo Lee ,  Xianmin Tang

IPC: C23C14/54 ,  C23C14/58 ,  C23C14/34 ,  H01L21/02

Abstract: Methods and apparatus for processing a substrate. The method, for example, includes directing a stream of material from a PVD source at a first non-perpendicular angle to selectively deposit the material on a top portion of one or more features on the substrate and form a first overhang and a second overhang extending beyond a third sidewall and a fourth sidewall that are arranged parallel and opposite to each other and at non-zero angles to a first sidewall and a second sidewall, the first sidewall and the second sidewall defining a length of the one or more features, and the third sidewall and fourth sidewall defining a width of the one or more features; performing an etch process to selectively remove some of the first sidewall and the second sidewall while keeping the third sidewall and fourth sidewall in intact and maintaining the width of the one or more features.

公开(公告)号：US12284803B2

公开(公告)日：2025-04-22

申请号：US17688602

申请日：2022-03-07

Applicant: Applied Materials, Inc.

Inventor： Nicolas Louis Breil ,  Fredrick Fishburn ,  Byeong Chan Lee

IPC: H01L27/108 ,  H10B12/00

Abstract: The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.