Invention Grant
- Patent Title: Package on active silicon semiconductor packages
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Application No.: US16641922Application Date: 2017-09-28
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Publication No.: US11978727B2Publication Date: 2024-05-07
- Inventor: Wilfred Gomes , Sanka Ganesan , Doug Ingerly , Robert Sankman , Mark Bohr , Debendra Mallik
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/054038 2017.09.28
- International Announcement: WO2019/066859A 2019.04.04
- Date entered country: 2020-02-25
- Main IPC: H01L25/10
- IPC: H01L25/10 ; H01L25/00 ; H01L25/065

Abstract:
Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.
Public/Granted literature
- US20210013188A1 PACKAGE ON ACTIVE SILICON SEMICONDUCTOR PACKAGES Public/Granted day:2021-01-14
Information query
IPC分类: