公开(公告)号：US20240030142A1

公开(公告)日：2024-01-25

申请号：US18375867

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/367 ,  H01L23/3185 ,  H01L23/5386 ,  H01L24/16 ,  H01L23/5384 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11804426B2

公开(公告)日：2023-10-31

申请号：US17379724

申请日：2021-07-19

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  William James Lambert ,  Zhichao Zhang ,  Sri Chaitra Jyotsna Chavali ,  Stephen Andrew Smith ,  Michael James Hill ,  Zhenguo Jiang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H05K1/18 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H05K7/02 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/4832 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H05K1/181 ,  H05K7/023

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

公开(公告)号：US11756889B2

公开(公告)日：2023-09-12

申请号：US16534027

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Kevin McCarthy ,  Leigh M. Tribolet ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L2221/68354 ,  H01L2221/68372 ,  H01L2224/08225 ,  H01L2224/214 ,  H01L2224/80006 ,  H01L2224/80894 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/05442

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

公开(公告)号：US20220293327A1

公开(公告)日：2022-09-15

申请号：US17199005

申请日：2021-03-11

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Sri Chaitra Jyotsna Chavali ,  Robert L. Sankman ,  Anne Augustine ,  Kaladhar Radhakrishnan

IPC: H01F27/26 ,  H01F27/40 ,  H01F41/04

Abstract: An inductor can be formed in a coreless electronic substrate, such that the fabrication process does not result in the magnetic material used in the inductor leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming conductive vias with a lithographic process, rather than a standard laser process, in combination with panel planarization to prevent exposure of the magnetic material to the plating and/or etching solutions/chemistries.

公开(公告)号：US11430724B2

公开(公告)日：2022-08-30

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Robert L. Sankman ,  Robert Nickerson ,  Mitul Modi ,  Sanka Ganesan ,  Rajasekaran Swaminathan ,  Omkar Karhade ,  Shawna M. Liff ,  Amruthavalli Alur ,  Sri Chaitra J. Chavali

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US11387175B2

公开(公告)日：2022-07-12

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sanka Ganesan ,  Pilin Liu ,  Shawna Liff ,  Sri Chaitra Chavali ,  Sandeep Gaan ,  Jimin Yao ,  Aastha Uppal

IPC: H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532 ,  H01L23/498

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20210366862A1

公开(公告)日：2021-11-25

申请号：US17392598

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Zhaozhi Li ,  Sanka Ganesan ,  Debendra Mallik ,  Gregory Perry ,  Kuan H. Lu ,  Omkar Karhade ,  Shawna M. Liff

IPC: H01L23/00

Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.

公开(公告)号：US20200273811A1

公开(公告)日：2020-08-27

申请号：US16287665

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mitul Modi ,  Sanka Ganesan ,  Edvin Cetegen ,  Omkar Karhade ,  Ravindranath Mahajan ,  James C. Matayabas, Jr. ,  Jan Krajniak ,  Kumar Singh ,  Aastha Uppal

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/29 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56 ,  H01L23/532

Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US10037976B2

公开(公告)日：2018-07-31

申请号：US15704720

申请日：2017-09-14

Applicant: INTEL CORPORATION

Inventor： Sanka Ganesan ,  Bassam Ziadeh ,  Nitesh Nimkar

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L25/10 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/293 ,  H01L24/02 ,  H01L24/03 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0381 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/27 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/3301 ,  H01L2224/33106 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80903 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.