- Patent Title: Methods of reducing parasitic capacitance in semiconductor devices
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Application No.: US17350177Application Date: 2021-06-17
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Publication No.: US12009263B2Publication Date: 2024-06-11
- Inventor: Kai-Hsuan Lee , Feng-Cheng Yang , Yen-Ming Chen , Sai-Hooi Yeong
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- The original application number of the division: US16399553 2019.04.30
- Main IPC: H01L21/3105
- IPC: H01L21/3105 ; H01L21/285 ; H01L21/764 ; H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L29/66 ; H01L29/78

Abstract:
A semiconductor structure includes a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), an S/D contact disposed over the S/D feature, and a dielectric layer disposed over the S/D contact, where the S/D feature and the S/D contact are separated from the MG by a first air gap, where the dielectric layer partially fills the first air gap, and where a bottom portion of a bottom surface of the S/D contact is separated from a top portion of the S/D feature by a second air gap that is connected to the first air gap.
Public/Granted literature
- US20210313233A1 Methods of Reducing Parasitic Capacitance in Semiconductor Devices Public/Granted day:2021-10-07
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