Invention Grant
- Patent Title: Chip-scale package architectures containing a die back side metal and a solder thermal interface material
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Application No.: US17033080Application Date: 2020-09-25
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Publication No.: US12040246B2Publication Date: 2024-07-16
- Inventor: Susmriti Das Mahapatra , Malavarayan Sankarasubramanian , Shenavia Howell , John Harper , Mitul Modi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L23/367
- IPC: H01L23/367 ; H01L21/48 ; H01L21/50 ; H01L21/768 ; H01L23/00 ; H01L23/36 ; H01L23/373 ; H01L23/42 ; H01L23/488 ; H01L21/60
Abstract:
An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.
Public/Granted literature
Information query
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