- 专利标题： Method and apparatus for implied bit handling in floating point multiplication
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申请号： US17987020申请日： 2022-11-15
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公开(公告)号： US12045172B2公开(公告)日： 2024-07-23
- 发明人: Mujibur Rahman , Timothy David Anderson
- 申请人： Texas Instruments Incorporated
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Michael T. Gabrik; Frank D. Cimino
- 主分类号： G06F7/487
- IPC分类号： G06F7/487 ; G06F7/24 ; G06F7/499 ; G06F7/53 ; G06F7/57 ; G06F9/30 ; G06F9/32 ; G06F9/345 ; G06F9/38 ; G06F9/48 ; G06F11/00 ; G06F11/10 ; G06F12/0862 ; G06F12/0875 ; G06F12/0897 ; G06F12/1009 ; G06F12/1045 ; G06F17/16 ; H03H17/06
摘要：
A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.
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