Invention Grant
- Patent Title: Multi-dimensional FFT computation pipelined hardware architecture using Radix-3 and Radix-2
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Application No.: US17351699Application Date: 2021-06-18
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Publication No.: US12045582B2Publication Date: 2024-07-23
- Inventor: Pankaj Gupta , Karthik Subburaj , Sujaata Ramalingam , Karthik Ramasubramanian , Indu Prathapan
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Michael T. Gabrik; Frank D. Cimino
- Priority: IN 2041050040 2020.11.17
- Main IPC: G06F7/49
- IPC: G06F7/49 ; G06F7/501 ; G06F17/14
Abstract:
A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.
Public/Granted literature
- US20220156044A1 MULTI-DIMENSIONAL FFT COMPUTATION PIPELINED HARDWARE ARCHITECTURE USING RADIX-3 AND RADIX-2² BUTTERFLIES Public/Granted day:2022-05-19
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