-
公开(公告)号：US20210105019A1
公开(公告)日：2021-04-08
申请号：US17063037
申请日：2020-10-05
发明人： Pankaj Gupta , Jawaharlal Tangudu , Ajai Paulose
IPC分类号： H03M1/10
摘要： A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.
-
公开(公告)号：US10901692B2
公开(公告)日：2021-01-26
申请号：US16237447
申请日：2018-12-31
发明人： Indu Prathapan , Puneet Sabbarwal , Pankaj Gupta
摘要： An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.
-
公开(公告)号：US20240356496A1
公开(公告)日：2024-10-24
申请号：US18615831
申请日：2024-03-25
发明人： Pankaj Gupta , Jawaharlal Tangudu , Manchi Sankalkar Ajay , Mathews John , Jaiganesh Balakrishnan , Neeraj Kumar Sharma
IPC分类号： H03F1/32
CPC分类号： H03F1/3247
摘要： An example apparatus includes: memory having a terminal, the memory to store machine-readable instructions and adjacent channel leakage data; and programmable circuitry having a terminal coupled to the terminal of the memory, the programmable circuitry to execute the machine-readable instructions to: determine a range of out-of-band frequencies responsive to adjacent channel leakage ratio data; generate weight values responsive to electromagnetic emissions within the range of out-of-band frequencies of a first signal; modify a pre-distortion function responsive to the weight values; and apply the modified pre-distortion function to generate a second signal, the second signal to exhibit fewer emissions in the range of out-of-band frequencies than the first signal during transmission.
-
公开(公告)号：US20240143282A1
公开(公告)日：2024-05-02
申请号：US17977813
申请日：2022-10-31
发明人： Mathews John , Jawaharlal Tangudu , Pankaj Gaur , Divyansh Jain , Pankaj Gupta
摘要： In described examples, an integrated circuit includes an output terminal coupled to an input of a power amplifier, a feedback terminal coupled to an output of the power amplifier, a data terminal that receives a data stream, and a digital pre-distortion (DPD) circuit. The DPD circuit includes a capture circuit, a DPD estimator responsive to the data stream and the feedback terminal, and a DPD corrector responsive to the DPD estimator. The DPD estimator includes an instruction memory configured to store instructions and a vector arithmetic processing unit (APU) coupled to the instruction memory. The vector APU includes vector memories, vector arithmetic blocks, and an instruction decode block. The vector arithmetic blocks include vector addition blocks and vector multiplication blocks. The instruction decode block is configured to cause the vector APU to perform complex domain vector arithmetic on vectors stored in the vector memories in response to the instructions.
-
公开(公告)号：US11579242B2
公开(公告)日：2023-02-14
申请号：US16442152
申请日：2019-06-14
IPC分类号： G01S7/02 , H04B15/02 , H04L27/10 , G01S7/35 , G01S13/34 , G01S13/58 , G01S13/42 , G01S13/931
摘要： A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.
-
公开(公告)号：US11239854B2
公开(公告)日：2022-02-01
申请号：US17061730
申请日：2020-10-02
发明人： Jawaharlal Tangudu , Pankaj Gupta , Sreenath Narayanan Potty , Ajai Paulose , Chandrasekhar Sriram , Mahesh Ravi Varma , Shabbar Abbasi Vejlani , Neeraj Shrivastava , Himanshu Varshney , Divyeshkumar Mahendrabhai Patel , Raju Kharataram Chaudhari
摘要： A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.
-
公开(公告)号：US11221397B2
公开(公告)日：2022-01-11
申请号：US16376515
申请日：2019-04-05
摘要： A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.
-
公开(公告)号：US20210149632A1
公开(公告)日：2021-05-20
申请号：US17156731
申请日：2021-01-25
发明人： Indu Prathapan , Puneet Sabbarwal , Pankaj Gupta
摘要： An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.
-
公开(公告)号：US10484224B2
公开(公告)日：2019-11-19
申请号：US15942614
申请日：2018-04-02
IPC分类号： H04L27/26
摘要： The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.
-
公开(公告)号：US10330773B2
公开(公告)日：2019-06-25
申请号：US15184715
申请日：2016-06-16
摘要： A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.021 秒)
