Invention Grant
- Patent Title: Package formation methods including coupling a molded routing layer to an integrated routing layer
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Application No.: US17991503Application Date: 2022-11-21
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Publication No.: US12057364B2Publication Date: 2024-08-06
- Inventor: Lizabeth Keser , Thomas Ort , Thomas Wagner , Bernd Waidhas
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- The original application number of the division: US16855418 2020.04.22
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/48 ; H01L21/56 ; H01L21/66 ; H01L21/78 ; H01L23/00 ; H01L23/538
Abstract:
A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
Public/Granted literature
- US20230090265A1 FAN OUT PACKAGE AND METHODS Public/Granted day:2023-03-23
Information query
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