公开(公告)号：US20250157941A1

公开(公告)日：2025-05-15

申请号：US19025226

申请日：2025-01-16

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

公开(公告)号：US12191571B2

公开(公告)日：2025-01-07

申请号：US17323278

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC: H01Q19/06 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/66 ,  H01Q1/48 ,  H01Q15/08

Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US20240355697A1

公开(公告)日：2024-10-24

申请号：US18762478

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3192 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L23/3128 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/95001

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US20230317681A1

公开(公告)日：2023-10-05

申请号：US17709481

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sonja Koller ,  Vishnu Prasad ,  Bernd Waidhas ,  Eduardo De Mesa ,  Lizabeth Keser ,  Thomas Wagner ,  Mohan Prashanth Javare Gowda ,  Abdallah Bacha ,  Jan Proschwitz

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/427 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3736 ,  H01L23/427 ,  H01L24/16 ,  H01L24/32 ,  H01L23/367 ,  H01L25/50 ,  H01L2225/06589 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2224/73203 ,  H01L2224/32245 ,  H01L2224/16146 ,  H01L2224/14152 ,  H01L2224/1416 ,  H01L24/14 ,  H01L24/73

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

公开(公告)号：US20230317551A1

公开(公告)日：2023-10-05

申请号：US17708890

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Vishnu Prasad ,  Abdallah Bacha ,  Mohan Prashanth Javare Gowda ,  Lizabeth Keser ,  Thomas Wagner ,  Bernd Waidhas ,  Sonja Koller ,  Eduardo De Mesa ,  Jan Proschwitz

IPC: H01L23/373 ,  H01L25/18 ,  H01L21/48

CPC classification number: H01L23/3736 ,  H01L25/18 ,  H01L21/4896

Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.

公开(公告)号：US11764187B2

公开(公告)日：2023-09-19

申请号：US16641241

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US20220294115A1

公开(公告)日：2022-09-15

申请号：US17831151

申请日：2022-06-02

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Sonja Koller ,  Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Stephan Stoecki ,  Thomas Wagner ,  Josef Hagn

IPC: H01Q9/04 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

公开(公告)号：US20220015244A1

公开(公告)日：2022-01-13

申请号：US17486462

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Sonja Koller ,  Bernd Waidhas

IPC: H05K3/34 ,  H01L23/498

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

公开(公告)号：US11177220B2

公开(公告)日：2021-11-16

申请号：US16490521

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Andreas Wolter ,  Bernd Waidhas ,  Thomas Wagner

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Electronics devices, having vertical and lateral redistribution interconnects, are disclosed. An electronics device comprises an electronics component (e.g., die, substrate, integrated device, etc.), a die(s), and a separately formed redistribution connection layer electrically coupling the die(s) to the electronics component. The redistribution connection layer comprises dielectric layers on either side of at least one redistribution layer. The dielectric layers comprise openings that expose contact pads of the at least one redistribution layer for electrically coupling die(s) and components to each other via the redistribution connection layer. The redistribution connection layer is flexible and wrap/folded around side edges of die(s) to minimize vertical vias. Various devices and associated processes are provided.

公开(公告)号：US20180157289A1

公开(公告)日：2018-06-07

申请号：US15870819

申请日：2018-01-12

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Dirk Plenkers ,  Hans-Joachim Barth ,  Bernd Waidhas ,  Yen Hsiang Chew ,  Kooi Chi Ooi ,  Howe Yin Loo

IPC: G06F1/16 ,  G02C11/00 ,  G02C5/14 ,  B29C39/02 ,  B29C65/48 ,  B29C39/10 ,  B29L31/34

CPC classification number: G06F1/163 ,  B29C39/021 ,  B29C39/10 ,  B29C65/4825 ,  B29L2031/3481 ,  G02C5/143 ,  G02C11/10

Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the users skin in the portion of the users body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the users body, the second electrode is arranged to not contact the users skin in the portion of the users body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.