Invention Grant
- Patent Title: In system test of chips in functional systems
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Application No.: US18348110Application Date: 2023-07-06
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Publication No.: US12078678B2Publication Date: 2024-09-03
- Inventor: Shantanu Sarangi , Jae Wu , Andi Skende , Rajith Mavila
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3177 ; G01R31/3181 ; G01R31/3185 ; G01R31/3187 ; G06F11/14 ; G06F11/22 ; G06F11/267 ; G06F11/27 ; G06F11/273 ; G06F11/36

Abstract:
Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.
Public/Granted literature
- US20230349970A1 IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS Public/Granted day:2023-11-02
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