公开(公告)号：US12078678B2

公开(公告)日：2024-09-03

申请号：US18348110

申请日：2023-07-06

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3181 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/14 ,  G06F11/22 ,  G06F11/267 ,  G06F11/27 ,  G06F11/273 ,  G06F11/36

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/318555 ,  G01R31/3187 ,  G06F11/1417 ,  G06F11/2268 ,  G06F11/2273 ,  G06F11/267 ,  G06F11/27 ,  G06F11/273 ,  G06F11/3688

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US11408934B2

公开(公告)日：2022-08-09

申请号：US16230929

申请日：2018-12-21

Applicant: Nvidia Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/14 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G01R31/3181 ,  G01R31/3185 ,  G06F11/273

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US20240132083A1

公开(公告)日：2024-04-25

申请号：US18048952

申请日：2022-10-23

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jae Wu ,  Shantanu Sarangi ,  Sailendra Chadalavada ,  Milind Sonawane ,  Chen Fang ,  Abilash Nerallapally

IPC: B60W50/02

CPC classification number: B60W50/0205 ,  B60W2050/0044

Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.

公开(公告)号：US20220382659A1

公开(公告)日：2022-12-01

申请号：US17883199

申请日：2022-08-08

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G06F11/27 ,  G06F11/267 ,  G06F11/22

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US20230349970A1

公开(公告)日：2023-11-02

申请号：US18348110

申请日：2023-07-06

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/14 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G01R31/3181 ,  G01R31/3185 ,  G06F11/273 ,  G06F11/267

CPC classification number: G01R31/31724 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/1417 ,  G06F11/3688 ,  G06F11/27 ,  G06F11/2268 ,  G01R31/31813 ,  G01R31/318555 ,  G06F11/273 ,  G06F11/2273 ,  G06F11/267

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US20220138387A1

公开(公告)日：2022-05-05

申请号：US17089864

申请日：2020-11-05

Applicant: Nvidia Corporation

Inventor： Kaushik Narayanun ,  Mahmut Yilmaz ,  Shantanu Sarangi ,  Jae Wu

IPC: G06F30/33 ,  G06F30/323 ,  G06F30/392 ,  G06T1/20

Abstract: The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

公开(公告)号：US11726139B2

公开(公告)日：2023-08-15

申请号：US17883199

申请日：2022-08-08

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/14 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G01R31/3181 ,  G06F11/267 ,  G01R31/3185 ,  G06F11/273

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/3187 ,  G01R31/31813 ,  G01R31/318555 ,  G06F11/1417 ,  G06F11/2268 ,  G06F11/2273 ,  G06F11/267 ,  G06F11/27 ,  G06F11/273 ,  G06F11/3688

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US20190195947A1

公开(公告)日：2019-06-27

申请号：US16230929

申请日：2018-12-21

Applicant: Nvidia Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G01R31/3181 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G06F11/14

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/3187 ,  G06F11/1417 ,  G06F11/2268 ,  G06F11/27 ,  G06F11/3688

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US12291219B2

公开(公告)日：2025-05-06

申请号：US18048952

申请日：2022-10-24

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jae Wu ,  Shantanu Sarangi ,  Sailendra Chadalavada ,  Milind Sonawane ,  Chen Fang ,  Abilash Nerallapally

IPC: B60W50/02 ,  B60W50/00

Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.

公开(公告)号：US20240227824A9

公开(公告)日：2024-07-11

申请号：US18048952

申请日：2022-10-24

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jae Wu ,  Shantanu Sarangi ,  Sailendra Chadalavada ,  Milind Sonawane ,  Chen Fang ,  Abilash Nerallapally

IPC: B60W50/02

CPC classification number: B60W50/0205 ,  B60W2050/0044

Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.