公开(公告)号：US11726139B2

公开(公告)日：2023-08-15

申请号：US17883199

申请日：2022-08-08

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/14 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G01R31/3181 ,  G06F11/267 ,  G01R31/3185 ,  G06F11/273

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/3187 ,  G01R31/31813 ,  G01R31/318555 ,  G06F11/1417 ,  G06F11/2268 ,  G06F11/2273 ,  G06F11/267 ,  G06F11/27 ,  G06F11/273 ,  G06F11/3688

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US20190195947A1

公开(公告)日：2019-06-27

申请号：US16230929

申请日：2018-12-21

Applicant: Nvidia Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G01R31/3181 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G06F11/14

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/3187 ,  G06F11/1417 ,  G06F11/2268 ,  G06F11/27 ,  G06F11/3688

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US12078678B2

公开(公告)日：2024-09-03

申请号：US18348110

申请日：2023-07-06

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3181 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/14 ,  G06F11/22 ,  G06F11/267 ,  G06F11/27 ,  G06F11/273 ,  G06F11/36

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/318555 ,  G01R31/3187 ,  G06F11/1417 ,  G06F11/2268 ,  G06F11/2273 ,  G06F11/267 ,  G06F11/27 ,  G06F11/273 ,  G06F11/3688

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US11408934B2

公开(公告)日：2022-08-09

申请号：US16230929

申请日：2018-12-21

Applicant: Nvidia Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/14 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G01R31/3181 ,  G01R31/3185 ,  G06F11/273

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US20220382659A1

公开(公告)日：2022-12-01

申请号：US17883199

申请日：2022-08-08

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G06F11/27 ,  G06F11/267 ,  G06F11/22

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US20230349970A1

公开(公告)日：2023-11-02

申请号：US18348110

申请日：2023-07-06

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/14 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G01R31/3181 ,  G01R31/3185 ,  G06F11/273 ,  G06F11/267

CPC classification number: G01R31/31724 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/1417 ,  G06F11/3688 ,  G06F11/27 ,  G06F11/2268 ,  G01R31/31813 ,  G01R31/318555 ,  G06F11/273 ,  G06F11/2273 ,  G06F11/267

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.