A path delay prediction method for an integrated circuit based on feature selection and deep learning. First, an integrated feature selection method based on filter methods and wrapper methods is established to determine an optimal feature subset. Timing information and physical topological information of a circuit are then extracted to be used as input features of a model, and local physical and timing expressions of cells in circuit paths are captured by means of the convolution calculation mechanism of a convolutional neural network. In addition, a residual network is used to calibrate a path delay. Compared with traditional back-end design processes, the path delay prediction method provided by the invention has remarkable advantages in prediction accuracy and efficiency and has great significance in accelerating the integrated circuit design process.