公开(公告)号：US11755807B2

公开(公告)日：2023-09-12

申请号：US18010131

申请日：2022-03-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng Cao ,  Kai Wang ,  Tai Yang ,  Wei Bao

IPC: G06F30/367 ,  G06N3/0442 ,  G06N3/0464 ,  G06N3/045 ,  G06F119/06 ,  G06F119/12

CPC classification number: G06F30/367 ,  G06N3/045 ,  G06N3/0442 ,  G06N3/0464 ,  G06F2119/06 ,  G06F2119/12

Abstract: Disclosed in the present invention is a method for predicting a delay at multiple corners for a digital integrated circuit, which is applicable to the problem of timing signoff at multiple corners. In the aspect of feature engineering, a path delay relationship at adjacent corners is extracted by using a dilated convolutional neural network (Dilated CNN), and learning is performed by using a bi-directional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) to obtain topology information of a path. Finally, prediction results of a path delay at a plurality of corners are obtained by using an output of a multi-gate mixture-of-experts network model (Multi-gate Mixture-of-Experts, MMoE). Compared with a conventional machine learning method, the present invention can achieve prediction with higher precision through more effective feature engineering processing in a case of low simulation overheads, and is of great significance for timing signoff at multiple corners of a digital integrated circuit.

公开(公告)号：US12093634B2

公开(公告)日：2024-09-17

申请号：US18567044

申请日：2023-01-03

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng Cao ,  Xu Cheng ,  Tai Yang

IPC: G06F30/398 ,  G06F30/27 ,  G06F30/33 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/392 ,  G06F30/3953

CPC classification number: G06F30/398 ,  G06F30/27 ,  G06F30/33 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/392 ,  G06F30/3953

Abstract: A path delay prediction method for an integrated circuit based on feature selection and deep learning. First, an integrated feature selection method based on filter methods and wrapper methods is established to determine an optimal feature subset. Timing information and physical topological information of a circuit are then extracted to be used as input features of a model, and local physical and timing expressions of cells in circuit paths are captured by means of the convolution calculation mechanism of a convolutional neural network. In addition, a residual network is used to calibrate a path delay. Compared with traditional back-end design processes, the path delay prediction method provided by the invention has remarkable advantages in prediction accuracy and efficiency and has great significance in accelerating the integrated circuit design process.

公开(公告)号：US12056428B1

公开(公告)日：2024-08-06

申请号：US18571739

申请日：2023-01-03

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng Cao ,  Guoqing He ,  Tai Yang

IPC: G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/3315 ,  G06F2119/12

Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.