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102 条记录 (耗时 0.027 秒)

    Memory instance reconfiguration using super leaf cells
    2.
    发明授权
    Memory instance reconfiguration using super leaf cells 有权

    公开(公告)号：US11836433B2

    公开(公告)日：2023-12-05

    申请号：US17592404

    申请日：2022-02-03

    申请人： Synopsys, Inc.

    发明人： John Edward Barth ,  Jeffrey C. Herbert ,  Matthew Christopher Lanahan

    IPC分类号： G06F30/39 ,  G06F30/3312 ,  G06F30/3315

    CPC分类号： G06F30/39 ,  G06F30/3312 ,  G06F30/3315

    摘要： A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

    Computer-readable recording medium storing timing library creation program, method of creating timing library, and timing analysis apparatus
    3.
    发明授权
    Computer-readable recording medium storing timing library creation program, method of creating timing library, and timing analysis apparatus 有权

    公开(公告)号：US11797741B2

    公开(公告)日：2023-10-24

    申请号：US17700576

    申请日：2022-03-22

    申请人： FUJITSU LIMITED

    发明人： Keisuke Nishida

    IPC分类号： G06F30/3315 ,  G06F111/10 ,  G06F119/12

    CPC分类号： G06F30/3315 ,  G06F2111/10 ,  G06F2119/12

    摘要： A non-transitory computer-readable recording medium storing a timing library creation program of causing a computer to execute processing, the processing including: extracting, from a delay variation database that stores delay variation values of gates included in circuit design data, a delay variation value, out of the delay valuation values matching to characteristics which are characteristics of one of signal paths in the circuit design data and which include a threshold voltage, a drive force, and a number of gate stages of the signal path; calculating an extended delay variation coefficient based on the extracted delay variation value and the characteristics; and creating, based on a basic timing library in which the delay variation value is not reflected and the extended delay variation coefficient, an extended timing library in which the delay variation value is reflected.

    Multi-PVT frequency prediction (multi-PVT FP) for statically timed designs through statistical regression
    7.
    发明授权
    Multi-PVT frequency prediction (multi-PVT FP) for statically timed designs through statistical regression 有权

    公开(公告)号：US11475194B1

    公开(公告)日：2022-10-18

    申请号：US16778537

    申请日：2020-01-31

    申请人： Apex Semiconductor

    发明人： Alfred Yeung ,  Minkyu Kim ,  Suresh Subramaniam ,  Pravin Chingudi

    IPC分类号： G06F30/3315 ,  G06F30/3308 ,  G06F119/12

    摘要： Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through statistical analysis. A design management component (DMC) can determine a trained model representing timing path properties and operating conditions of agnostic timing paths based on an analysis of vectorized data that represents timing path information associated with the agnostic timing paths. DMC can perform statistical regression on the vectorized data to facilitate training the trained model. A static timing analysis (STA) component can perform STA on design information associated with the integrated circuitry design and determine an operating condition of a timing path of the integrated circuitry design based on the STA. DMC can predict or determine at least one other operating condition associated with the integrated circuitry design based on the operating condition and the trained model.

    REINFORCEMENT LEARNING-BASED ADJUSTMENT OF DIGITAL CIRCUITS
    8.
    发明申请
    REINFORCEMENT LEARNING-BASED ADJUSTMENT OF DIGITAL CIRCUITS 有权

    公开(公告)号：US20220229960A1

    公开(公告)日：2022-07-21

    申请号：US17579490

    申请日：2022-01-19

    申请人： Synopsys, Inc.

    发明人： Siddhartha NATH ,  Vishal KHANDELWAL ,  Yi-Chen LU ,  Praveen GHANTA

    IPC分类号： G06F30/3315 ,  G06F30/27

    摘要： Systems and methods for adjusting a digital circuit design are described. For example, the method may include selecting a first path in the digital circuit design. The first path includes a plurality of gates. The method also includes generating a k-hop neighborhood graph of the first path, encoding the k-hop neighborhood graph into a state vector, and applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates. The method further includes changing the first gate based on the adjustment.

    MODELLING TIMING BEHAVIOR USING AUGMENTED SENSITIVITY DATA FOR PHYSICAL PARAMETERS
    9.
    发明申请
    MODELLING TIMING BEHAVIOR USING AUGMENTED SENSITIVITY DATA FOR PHYSICAL PARAMETERS 有权

    公开(公告)号：US20220171910A1

    公开(公告)日：2022-06-02

    申请号：US17540774

    申请日：2021-12-02

    申请人： Synopsys, Inc.

    发明人： Ruijing SHEN ,  Li DING

    IPC分类号： G06F30/3312 ,  G06F30/3315 ,  G06F30/31

    摘要： A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

    Reset crossing and clock crossing interface for integrated circuit generation
    10.
    发明授权
    Reset crossing and clock crossing interface for integrated circuit generation 有权

    公开(公告)号：US11321511B2

    公开(公告)日：2022-05-03

    申请号：US17157564

    申请日：2021-01-25

    申请人： SiFive, Inc.

    发明人： Henry Cook ,  Ernest L. Edgar ,  Ryan Macdonald ,  Wesley Waylon Terpstra

    IPC分类号： G06F30/327 ,  G06F30/333 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/396 ,  G06F30/398 ,  G06F119/12 ,  G06F115/02

    摘要： Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.