Invention Grant
- Patent Title: Defect detection during erase operations
-
Application No.: US17889578Application Date: 2022-08-17
-
Publication No.: US12094549B2Publication Date: 2024-09-17
- Inventor: Jun Xu , Kitae Park
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C29/12
- IPC: G11C29/12 ; G11C16/10 ; G11C16/14 ; G11C16/34

Abstract:
A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.
Public/Granted literature
- US20230067457A1 DEFECT DETECTION DURING ERASE OPERATIONS Public/Granted day:2023-03-02
Information query