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公开(公告)号：US20230067457A1
公开(公告)日：2023-03-02
申请号：US17889578
申请日：2022-08-17
发明人： Jun Xu , Kitae Park
摘要： A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.
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公开(公告)号：US20230063656A1
公开(公告)日：2023-03-02
申请号：US17591510
申请日：2022-02-02
发明人： Chulbum Kim , Brian Kwon , Erwin E. Yu , Kitae Park , Taehyun Kim
摘要： A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.
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公开(公告)号：US20230060943A1
公开(公告)日：2023-03-02
申请号：US17889648
申请日：2022-08-17
发明人： Jun Xu , Kitae Park
IPC分类号： G06F3/06
摘要： A system includes a memory device including a memory array and a processing device, operatively coupled with the memory array, to perform operations including causing defect management information to be obtained from the memory device. The defect management information includes status information with respect to a status of the memory array and supplemental defect management information associated with a media access operation performed with respect to the memory array. The operations further include analyzing the defect management information to determine a likelihood of defect with respect to the memory array, and identifying, based on the likelihood of defect, a defect status of the memory array.
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公开(公告)号：US20230326532A1
公开(公告)日：2023-10-12
申请号：US18117268
申请日：2023-03-03
发明人： Go Shikata , Kitae Park
摘要： A memory device having a memory array with a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines and control logic coupled with the memory array. The control logic perform operations including: determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count; adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.
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公开(公告)号：US20230068482A1
公开(公告)日：2023-03-02
申请号：US17464289
申请日：2021-09-01
发明人： Sheyang Ning , Kitae Park
IPC分类号： G06F3/06
摘要： A method includes performing a first memory operation having a first type on a location of a memory component. The method further includes, responsive to receiving an access request to perform a second memory operation having a second type on the location, preventing, subsequent to completion of the first memory operation, the second memory operation from being performed for a period of time corresponding to a particular time interval associated with the first type and a second type.
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公开(公告)号：US12094549B2
公开(公告)日：2024-09-17
申请号：US17889578
申请日：2022-08-17
发明人： Jun Xu , Kitae Park
CPC分类号： G11C29/12 , G11C16/10 , G11C16/14 , G11C16/3445 , G11C2029/1202 , G11C2029/1204
摘要： A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.
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公开(公告)号：US11942159B2
公开(公告)日：2024-03-26
申请号：US17591510
申请日：2022-02-02
发明人： Chulbum Kim , Brian Kwon , Erwin E. Yu , Kitae Park , Taehyun Kim
CPC分类号： G11C16/14 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/225 , G11C16/32
摘要： A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.
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公开(公告)号：US20240062786A1
公开(公告)日：2024-02-22
申请号：US18228148
申请日：2023-07-31
发明人： Kitae Park , Aaron Yip
IPC分类号： G11C5/06 , H10B80/00 , H01L23/528 , G11C16/08 , H01L25/065
CPC分类号： G11C5/063 , H10B80/00 , H01L23/5283 , G11C16/08 , H01L25/0655
摘要： A memory device includes a memory array die corresponding to a memory array, an access circuitry die corresponding to peripheral circuitry to support access operations with respect to the memory array, and a bonding layer disposed between the memory array die and the access circuitry die to form an interconnection between the memory array and the access circuitry. In some embodiments, the access circuitry die further integrates a local media controller corresponding to the memory array. In some embodiments, the local media controller is located external to the access circuitry die.
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公开(公告)号：US20240006007A1
公开(公告)日：2024-01-04
申请号：US17856827
申请日：2022-07-01
发明人： Kitae Park
CPC分类号： G11C29/10 , G06F3/0619 , G06F3/0632 , G06F3/0673
摘要： Apparatuses, systems, and methods for predetermined pattern program operations are described according to embodiments of the present disclosure. One example method can include determining a portion of a memory device is invalid and performing a predetermined pattern program operation on the portion of the memory device in response to determining the portion of the memory device is invalid.
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10.发明公开公开(公告)号：US20240203508A1
公开(公告)日：2024-06-20
申请号：US18589730
申请日：2024-02-28
发明人： Chulbum Kim , Brian Kwon , Erwin E. Yu , Kitae Park , Taehyun Kim
CPC分类号： G11C16/14 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/225 , G11C16/32
摘要： A memory device includes a memory array comprising memory cells and control logic operatively coupled with the memory array. The control logic causes, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of the memory array. The control logic tracks a number of suspend commands received from a processing device, including suspend commands received while memory cells of the one or more sub-blocks are being erased. The control logic causes, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation. The control logic, in response to the number of suspend commands satisfying a threshold criterion, alerts the processing device to terminate sending suspend commands.
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