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公开(公告)号：US12249381B2
公开(公告)日：2025-03-11
申请号：US18117268
申请日：2023-03-03
Applicant: Micron Technology, Inc.
Inventor： Go Shikata , Kitae Park
Abstract: A memory device having a memory array with a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines and control logic coupled with the memory array. The control logic perform operations including: determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count; adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.
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公开(公告)号：US20250046389A1
公开(公告)日：2025-02-06
申请号：US18924615
申请日：2024-10-23
Applicant: Micron Technology, Inc.
Inventor： Kitae Park
Abstract: Apparatuses, systems, and methods for predetermined pattern program operations are described according to embodiments of the present disclosure. One example method can include determining a portion of a memory device is invalid and performing a predetermined pattern program operation on the portion of the memory device in response to determining the portion of the memory device is invalid.
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公开(公告)号：US20240404615A1
公开(公告)日：2024-12-05
申请号：US18800670
申请日：2024-08-12
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Kitae Park
Abstract: A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including initiating an erase operation performed with respect to the memory array, identifying, between a pair of components of the memory array, at least one current differential indicative of at least one defect with respect to at least one failure point of the memory array, and causing an indication of the at least one defect to be generated. The erase operation includes a select gate scan sub-operation.
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公开(公告)号：US20230067457A1
公开(公告)日：2023-03-02
申请号：US17889578
申请日：2022-08-17
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Kitae Park
Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.
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公开(公告)号：US20230063656A1
公开(公告)日：2023-03-02
申请号：US17591510
申请日：2022-02-02
Applicant: Micron Technology, Inc.
Inventor： Chulbum Kim , Brian Kwon , Erwin E. Yu , Kitae Park , Taehyun Kim
Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.
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Patent Agency Ranking
公开(公告)号：US20230060943A1
公开(公告)日：2023-03-02
申请号：US17889648
申请日：2022-08-17
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Kitae Park
IPC: G06F3/06
Abstract: A system includes a memory device including a memory array and a processing device, operatively coupled with the memory array, to perform operations including causing defect management information to be obtained from the memory device. The defect management information includes status information with respect to a status of the memory array and supplemental defect management information associated with a media access operation performed with respect to the memory array. The operations further include analyzing the defect management information to determine a likelihood of defect with respect to the memory array, and identifying, based on the likelihood of defect, a defect status of the memory array.
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公开(公告)号：US20230326532A1
公开(公告)日：2023-10-12
申请号：US18117268
申请日：2023-03-03
Applicant: Micron Technology, Inc.
Inventor： Go Shikata , Kitae Park
Abstract: A memory device having a memory array with a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines and control logic coupled with the memory array. The control logic perform operations including: determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count; adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.
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公开(公告)号：US20230068482A1
公开(公告)日：2023-03-02
申请号：US17464289
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Kitae Park
IPC: G06F3/06
Abstract: A method includes performing a first memory operation having a first type on a location of a memory component. The method further includes, responsive to receiving an access request to perform a second memory operation having a second type on the location, preventing, subsequent to completion of the first memory operation, the second memory operation from being performed for a period of time corresponding to a particular time interval associated with the first type and a second type.
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公开(公告)号：US12154640B2
公开(公告)日：2024-11-26
申请号：US17856827
申请日：2022-07-01
Applicant: Micron Technology, Inc.
Inventor： Kitae Park
Abstract: Apparatuses, systems, and methods for predetermined pattern program operations are described according to embodiments of the present disclosure. One example method can include determining a portion of a memory device is invalid and performing a predetermined pattern program operation on the portion of the memory device in response to determining the portion of the memory device is invalid.
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公开(公告)号：US12094549B2
公开(公告)日：2024-09-17
申请号：US17889578
申请日：2022-08-17
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Kitae Park
CPC classification number: G11C29/12 , G11C16/10 , G11C16/14 , G11C16/3445 , G11C2029/1202 , G11C2029/1204
Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.
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