Invention Grant
- Patent Title: Rule check violation prediction systems and methods
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Application No.: US18447455Application Date: 2023-08-10
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Publication No.: US12106034B2Publication Date: 2024-10-01
- Inventor: Yi-Lin Chuang , Henry Lin , Szu-Ju Huang , Yin-An Chen , Amos Hong
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Seed IP Law Group LLP
- The original application number of the division: US16400664 2019.05.01
- Main IPC: G06F30/398
- IPC: G06F30/398 ; G06F30/327 ; G06F30/392 ; G06F30/394 ; G06N20/00

Abstract:
Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.
Public/Granted literature
- US20230385521A1 DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS Public/Granted day:2023-11-30
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