Invention Grant
- Patent Title: Loop support extensions
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Application No.: US17134367Application Date: 2020-12-26
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Publication No.: US12112171B2Publication Date: 2024-10-08
- Inventor: Anant Nori , Shankar Balachandran , Sreenivas Subramoney , Joydeep Rakshit , Vedvyas Shanbhogue , Avishaii Abuhatzera , Belliappa Kuttanna
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: NICHOLSON DE VOS WEBSTER & ELLIOTT LLP
- Main IPC: G06F8/41
- IPC: G06F8/41 ; G06F9/30 ; G06F9/38 ; G06F9/48

Abstract:
Techniques for processing loops are described. An exemplary apparatus at least includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions; and execution circuitry to perform the operation as indicated by the opcode.
Public/Granted literature
- US20220100514A1 LOOP SUPPORT EXTENSIONS Public/Granted day:2022-03-31
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