公开(公告)号：US12112171B2

公开(公告)日：2024-10-08

申请号：US17134367

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Anant Nori ,  Shankar Balachandran ,  Sreenivas Subramoney ,  Joydeep Rakshit ,  Vedvyas Shanbhogue ,  Avishaii Abuhatzera ,  Belliappa Kuttanna

IPC: G06F8/41 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/30145 ,  G06F9/30065 ,  G06F9/3836 ,  G06F9/4881

Abstract: Techniques for processing loops are described. An exemplary apparatus at least includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions; and execution circuitry to perform the operation as indicated by the opcode.

公开(公告)号：US20200226203A1

公开(公告)日：2020-07-16

申请号：US16833210

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Biji George ,  Om Ji Omer ,  Dipan Kumar Mandal ,  Cormac Brick ,  Lance Hacking ,  Sreenivas Subramoney ,  Belliappa Kuttanna

IPC: G06F17/16

Abstract: A disclosed apparatus to multiply matrices includes a compute engine. The compute engine includes multipliers in a two dimensional array that has a plurality of array locations defined by columns and rows. The apparatus also includes a plurality of adders in columns. A broadcast interconnect between a cache and the multipliers broadcasts a first set of operand data elements to multipliers in the rows of the array. A unicast interconnect unicasts a second set of operands between a data buffer and the multipliers. The multipliers multiply the operands to generate a plurality of outputs, and the adders add the outputs generated by the multipliers.

公开(公告)号：US11347828B2

公开(公告)日：2022-05-31

申请号：US16833210

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Biji George ,  Om Ji Omer ,  Dipan Kumar Mandal ,  Cormac Brick ,  Lance Hacking ,  Sreenivas Subramoney ,  Belliappa Kuttanna

IPC: G06F17/16

Abstract: A disclosed apparatus to multiply matrices includes a compute engine. The compute engine includes multipliers in a two dimensional array that has a plurality of array locations defined by columns and rows. The apparatus also includes a plurality of adders in columns. A broadcast interconnect between a cache and the multipliers broadcasts a first set of operand data elements to multipliers in the rows of the array. A unicast interconnect unicasts a second set of operands between a data buffer and the multipliers. The multipliers multiply the operands to generate a plurality of outputs, and the adders add the outputs generated by the multipliers.

公开(公告)号：US10181171B2

公开(公告)日：2019-01-15

申请号：US14085778

申请日：2013-11-20

Applicant: Intel Corporation

Inventor： Eric Sprangle ,  Matt Craighead ,  Chris Goodman ,  Belliappa Kuttanna

IPC: G06T1/00 ,  G06T1/20 ,  G06F15/00 ,  G06F15/16 ,  G06F15/167

Abstract: A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.