Invention Grant
- Patent Title: Transistor integration on a silicon-on-insulator substrate
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Application No.: US17830830Application Date: 2022-06-02
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Publication No.: US12113070B2Publication Date: 2024-10-08
- Inventor: Peter Baars , Viorel Ontalus , Ketankumar H. Tailor , Michael Zier , Crystal R. Kenney , Judson Holt
- Applicant: GlobalFoundries U.S. Inc.
- Applicant Address: US NY Malta
- Assignee: GlobalFoundries U.S. Inc.
- Current Assignee: GlobalFoundries U.S. Inc.
- Current Assignee Address: US NY Malta
- Agency: Thompson Hine LLP
- Agent Francois Pagette
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/84 ; H01L29/66

Abstract:
Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.
Public/Granted literature
- US20230395607A1 TRANSISTOR INTEGRATION ON A SILICON-ON-INSULATOR SUBSTRATE Public/Granted day:2023-12-07
Information query
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