公开(公告)号：US20240170561A1

公开(公告)日：2024-05-23

申请号：US17990931

申请日：2022-11-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Jeffrey Johnson ,  Viorel Ontalus ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7378 ,  H01L29/0817 ,  H01L29/66242

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an emitter, a collector including a first section, a second section, and a third section positioned in a first direction between the first section and the second section, and an intrinsic base disposed in a second direction between the emitter and the third section of the collector. The structure further comprises a stress layer including a section positioned to overlap with the emitter, the intrinsic base, and the collector. The section of the stress layer is surrounded by a perimeter, and the first and second sections of the collector are each positioned adjacent to the perimeter of the stress layer.

公开(公告)号：US11217685B2

公开(公告)日：2022-01-04

申请号：US16909376

申请日：2020-06-23

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Herbert Ho ,  Vibhor Jain ,  John J. Pekarik ,  Claude Ortolland ,  Judson R. Holt ,  Qizhi Liu ,  Viorel Ontalus

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

公开(公告)号：US12113070B2

公开(公告)日：2024-10-08

申请号：US17830830

申请日：2022-06-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Viorel Ontalus ,  Ketankumar H. Tailor ,  Michael Zier ,  Crystal R. Kenney ,  Judson Holt

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L29/66242

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

公开(公告)号：US11056533B1

公开(公告)日：2021-07-06

申请号：US16804952

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Viorel Ontalus

IPC: H01L27/20 ,  H01L27/082 ,  H01L29/73

Abstract: One illustrative device disclosed herein includes a semiconductor substrate, a bipolar junction transistor (BJT) device that comprises a collector, a base and an emitter, at least one piezoelectric structure comprising a piezoelectric material positioned adjacent the BJT device, and at least first and second conductive contact structures that are conductively coupled to the piezoelectric structure.

公开(公告)号：US11916135B2

公开(公告)日：2024-02-27

申请号：US17587347

申请日：2022-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Viorel Ontalus ,  Justin C. Long ,  Robert K. Baiocco

IPC: H01L29/73 ,  H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/66287

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region in a semiconductor substrate; a base region adjacent to the collector region; and an emitter extending above the base region and comprising semiconductor material and a hardmask surrounding a lower portion of the semiconductor material.

公开(公告)号：US20230395607A1

公开(公告)日：2023-12-07

申请号：US17830830

申请日：2022-06-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Viorel Ontalus ,  Ketankumar H. Tailor ,  Michael Zier ,  Crystal R. Kenney ,  Judson Holt

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L29/66242

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

公开(公告)号：US11810951B2

公开(公告)日：2023-11-07

申请号：US17552386

申请日：2021-12-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Viorel Ontalus

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/66568 ,  H01L29/7848 ,  H01L29/78618

Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.

公开(公告)号：US20230197783A1

公开(公告)日：2023-06-22

申请号：US17552386

申请日：2021-12-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Viorel Ontalus

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/7848 ,  H01L29/66568 ,  H01L29/0653

Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.