公开(公告)号：US11532742B2

公开(公告)日：2022-12-20

申请号：US17206195

申请日：2021-03-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ketankumar Harishbhai Tailor ,  Peter Baars

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66

Abstract: An integrated circuit (IC) structure and a field plate are disclosed. The IC structure and field plate may find advantageous application with, for example, extended drain metal-oxide semiconductor (EDMOS) transistors. The IC structure includes a transistor including a metal gate structure and a drain extension region extending laterally from partially under the metal gate structure to a drain region. A metal field plate is over the drain extension region. Due to being formed simultaneously as part of a gate-last formation approach, the metal field plate has an upper surface coplanar with an upper surface of the metal gate structure. A field plate contact may be on the metal field plate.

公开(公告)号：US12113070B2

公开(公告)日：2024-10-08

申请号：US17830830

申请日：2022-06-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Viorel Ontalus ,  Ketankumar H. Tailor ,  Michael Zier ,  Crystal R. Kenney ,  Judson Holt

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L29/66242

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

公开(公告)号：US20230290829A1

公开(公告)日：2023-09-14

申请号：US17804201

申请日：2022-05-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Alexander M. Derrickson ,  Ketankumar Harishbhai Tailor ,  Zhixing Zhao ,  Judson R. Holt

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/1004 ,  H01L29/66234 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

公开(公告)号：US20220093751A1

公开(公告)日：2022-03-24

申请号：US17029446

申请日：2020-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ketankumar H. Tailor ,  Peter Baars ,  Ruchil K. Jain

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49

Abstract: Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.

公开(公告)号：US11195935B2

公开(公告)日：2021-12-07

申请号：US16531617

申请日：2019-08-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/266 ,  H01L27/11 ,  H01L21/3105 ,  H01L29/786 ,  H01L29/08 ,  H01L21/762

Abstract: A semiconductor device is disclosed including a gate electrode structure and raised drain and source regions that extend to a first height level and a sidewall spacer element positioned adjacent the sidewalls of the gate electrode structure between the raised drain and source regions and the gate electrode structure. The sidewall spacer element includes an upper portion that extends above the first height level wherein an inner part of the spacer element faces the gate electrode structure and extends to a second height level that is less than a third height level of an outer part of the upper portion of the spacer element.

公开(公告)号：US11888062B2

公开(公告)日：2024-01-30

申请号：US17491850

申请日：2021-10-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Felix Holzmüller ,  Ruchil K. Jain ,  Peter Baars

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/7816 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate containing a first semiconductor material, a source region and a drain region in the semiconductor substrate, a gate electrode positioned in a lateral direction between the source region and the drain region, and a semiconductor layer positioned on the semiconductor substrate. The semiconductor layer contains a second semiconductor material that differs in composition from the first semiconductor material. The gate electrode includes a first section positioned in a vertical direction over the semiconductor layer and a second section positioned in the vertical direction over the semiconductor substrate.

公开(公告)号：US20230395607A1

公开(公告)日：2023-12-07

申请号：US17830830

申请日：2022-06-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Viorel Ontalus ,  Ketankumar H. Tailor ,  Michael Zier ,  Crystal R. Kenney ,  Judson Holt

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L29/66242

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

公开(公告)号：US11217678B2

公开(公告)日：2022-01-04

申请号：US16680196

申请日：2019-11-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US10923579B2

公开(公告)日：2021-02-16

申请号：US16854552

申请日：2020-04-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L21/285 ,  H01L27/12 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/8234

Abstract: A device including an SOI substrate and an isolation structure positioned at least partially in a trench that extends through a buried insulation layer and into a semiconductor bulk substrate of the SOI substrate is disclosed. The isolation structure includes a first dielectric layer positioned in a lower portion of the trench, a first material layer positioned above the first dielectric layer, the first material layer having a material different from a material of the first dielectric layer, and a second dielectric layer positioned above the first material layer, the second dielectric layer having a material different from the material of the first material layer.

公开(公告)号：US11916109B2

公开(公告)日：2024-02-27

申请号：US17804201

申请日：2022-05-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Alexander M. Derrickson ,  Ketankumar Harishbhai Tailor ,  Zhixing Zhao ,  Judson R. Holt

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/1004 ,  H01L29/66234 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.