Invention Grant
- Patent Title: Processor power management
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Application No.: US18339827Application Date: 2023-06-22
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Publication No.: US12124310B2Publication Date: 2024-10-22
- Inventor: Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: JAFFERY WATSON MENDONSA & HAMILTON LLP
- Main IPC: G09G3/06
- IPC: G09G3/06 ; G06F1/3203 ; G06F1/3209 ; G06F1/3212 ; G06F1/3218 ; G06F1/3231 ; G06F1/324 ; G06F3/01 ; G06F11/07 ; G06F11/30 ; H04W52/02 ; H04M1/72448

Abstract:
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20230418355A1 PROCESSOR POWER MANAGEMENT Public/Granted day:2023-12-28
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