- 专利标题: Processor power management
-
申请号: US18339827申请日: 2023-06-22
-
公开(公告)号: US12124310B2公开(公告)日: 2024-10-22
- 发明人: Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 代理机构: JAFFERY WATSON MENDONSA & HAMILTON LLP
- 主分类号: G09G3/06
- IPC分类号: G09G3/06 ; G06F1/3203 ; G06F1/3209 ; G06F1/3212 ; G06F1/3218 ; G06F1/3231 ; G06F1/324 ; G06F3/01 ; G06F11/07 ; G06F11/30 ; H04W52/02 ; H04M1/72448
摘要:
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
公开/授权文献
- US20230418355A1 PROCESSOR POWER MANAGEMENT 公开/授权日:2023-12-28
信息查询
IPC分类: