-
公开(公告)号：US20230418355A1
公开(公告)日：2023-12-28
申请号：US18339827
申请日：2023-06-22
Applicant: INTEL CORPORATION
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
IPC: G06F1/3209 , H04W52/02 , G06F1/324 , G06F1/3203 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F3/01 , G06F11/07 , G06F11/30
CPC classification number: G06F1/3209 , H04W52/0258 , G06F1/324 , G06F1/3203 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F3/01 , G06F11/0781 , G06F11/3062 , Y02D10/00 , Y02D30/70 , H04M1/72448
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US20220262059A1
公开(公告)日：2022-08-18
申请号：US17591166
申请日：2022-02-02
Applicant: Intel Corporation
Inventor： Devan Burke , Adam T. Lake , Jeffery S. Boles , John H. Feit , Karthik Vaidyanathan , Abhishek R. Appu , Joydeep Ray , Subramaniam Maiyuran , Altug Koker , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Eric J. Hoekstra , Gabor Liktor , Jonathan Kennedy , Slawomir Grajewski , Elmoustapha Ould-Ahmed-Vall
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
-
公开(公告)号：US20200241622A1
公开(公告)日：2020-07-30
申请号：US16782791
申请日：2020-02-05
Applicant: INTEL CORPORATION
Inventor： Abhishek R. Appu , Altug Koker , Eric J. Hoekstra , Kiran C. Veernapu , Prasoonkumar Surti , Vasanth Ranganathan , Kamal Sinha , Balaji Vembu , Eric J. Asperheim , Sanjeev S. Jahagirdar , Joydeep Ray
IPC: G06F1/3225 , G06F1/3234
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US10558254B2
公开(公告)日：2020-02-11
申请号：US15477042
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , Eric J. Hoekstra , Kiran C. Veernapu , Prasoonkumar Surti , Vasanth Ranganathan , Kamal Sinha , Balaji Vembu , Eric J. Asperheim , Sanjeev S. Jahagirdar , Joydeep Ray
IPC: G06F3/06 , G06F1/3225 , G06F1/3234
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US20180308197A1
公开(公告)日：2018-10-25
申请号：US15493420
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , Subramaniam M. Maiyuran , Abhishek R. Appu , Joydeep Ray , Altug Koker , James A. Valerio , Eric J. Hoekstra , Arthur D. Hunter, JR.
CPC classification number: G06T1/20 , G06F9/223 , G06F9/4496 , G06T15/04
Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
-
Patent Agency Ranking
公开(公告)号：US20180308196A1
公开(公告)日：2018-10-25
申请号：US15493352
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Joydeep Ray , Abhishek R. Appu , Subramaniam M. Maiyuran , Eric J. Hoekstra , Prasoonkumar Surti , Balaji Vembu , Altug Koker
CPC classification number: G06T1/20 , G06F9/4831 , G06F9/4881 , G06F9/505 , G06T2210/52
Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.
-
公开(公告)号：US20180284868A1
公开(公告)日：2018-10-04
申请号：US15477029
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US12124310B2
公开(公告)日：2024-10-22
申请号：US18339827
申请日：2023-06-22
Applicant: INTEL CORPORATION
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
IPC: G09G3/06 , G06F1/3203 , G06F1/3209 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F1/324 , G06F3/01 , G06F11/07 , G06F11/30 , H04W52/02 , H04M1/72448
CPC classification number: G06F1/3209 , G06F1/3203 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F1/324 , G06F3/01 , G06F11/0781 , G06F11/3062 , H04W52/0258 , H04M1/72448 , Y02D10/00 , Y02D30/70
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US11507375B2
公开(公告)日：2022-11-22
申请号：US17319056
申请日：2021-05-12
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US11257274B2
公开(公告)日：2022-02-22
申请号：US16887439
申请日：2020-05-29
Applicant: Intel Corporation
Inventor： Devan Burke , Adam T. Lake , Jeffery S. Boles , John H. Feit , Karthik Vaidyanathan , Abhishek R. Appu , Joydeep Ray , Subramaniam Maiyuran , Altug Koker , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Eric J. Hoekstra , Gabor Liktor , Jonathan Kennedy , Slawomir Grajewski , Elmoustapha Ould-Ahmed-Vall
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
-
-
-
-
-
-
-
-
-
Search Results
40
records
(took 0.02 seconds)
