Invention Grant
- Patent Title: Method of manufacturing semiconductor device with improved gate insulation step
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Application No.: US17500297Application Date: 2021-10-13
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Publication No.: US12137556B2Publication Date: 2024-11-05
- Inventor: Yuto Omizu
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Rimon P.C.
- Priority: JP2020-174301 20201016
- Main IPC: H10B41/35
- IPC: H10B41/35 ; H01L27/12 ; H10B43/35

Abstract:
A first insulating film is formed on a semiconductor substrate in each of a first region in which a memory transistor is to be formed, a second region in which a selection transistor is to be formed, a third region in which a high-withstand-voltage transistor is to be formed, and a fourth region in which a low-withstand-voltage transistor is to be formed. Subsequently, the first insulating film in each of the first and second regions is removed. A second insulating film is formed on the semiconductor substrate in each of the first and second regions. A third insulating film having a trap level is formed on the second insulating film. The third insulating film in the second region and the second insulating film in the second region are removed. A fourth insulating film is formed on the third insulating film and on the semiconductor substrate in the second region.
Public/Granted literature
- US20220123000A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2022-04-21
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