Invention Grant
- Patent Title: Processor with macro-instruction achieving zero-latency data movement
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Application No.: US17361244Application Date: 2021-06-28
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Publication No.: US12153921B2Publication Date: 2024-11-26
- Inventor: Matthew Brandon Gately , Eric Jonathan Deal , Mark Willard Johnson , Daniel Thomas Riedler
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Zagorin Cave LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/345 ; G06F9/38
Abstract:
An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.
Public/Granted literature
- US20220413850A1 Apparatus for Processor with Macro-Instruction and Associated Methods Public/Granted day:2022-12-29
Information query
