专利检索 ap:("Silicon Laboratories Inc.") AND inv:"Mark Willard Johnson" 第 1 页

1.

发明授权
Array processor using programmable per-dimension size values and programmable per-dimension stride values for memory configuration 有权

公开(公告)号：US12086597B2

公开(公告)日：2024-09-10

申请号：US17361250

申请日：2021-06-28

申请人： Silicon Laboratories Inc.

发明人： Matthew Brandon Gately , Eric Jonathan Deal , Mark Willard Johnson

IPC分类号： G06F9/32 , G06F9/345

CPC分类号： G06F9/325 , G06F9/3455

摘要： An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.

2.

发明申请
Apparatus for Memory Configuration for Array Processor and Associated Methods 有权

公开(公告)号：US20220414050A1

公开(公告)日：2022-12-29

申请号：US17361250

申请日：2021-06-28

申请人： Silicon Laboratories Inc.

发明人： Matthew Brandon Gately , Eric Jonathan Deal , Mark Willard Johnson

IPC分类号： G06F15/173 , G06F9/38

摘要： An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.

3.

发明申请
Apparatus for Array Processor and Associated Methods 有权

公开(公告)号：US20220414049A1

公开(公告)日：2022-12-29

申请号：US17361240

申请日：2021-06-28

申请人： Silicon Laboratories Inc.

发明人： Matthew Brandon Gately , Eric Jonathan Deal , Mark Willard Johnson , Sebastian Ahmed

IPC分类号： G06F15/173 , G06F9/38

摘要： An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values.

4.

发明授权
Array processor having an instruction sequencer including a program state controller and loop controllers 有权

公开(公告)号：US12079630B2

公开(公告)日：2024-09-03

申请号：US17361240

申请日：2021-06-28

申请人： Silicon Laboratories Inc.

发明人： Matthew Brandon Gately , Eric Jonathan Deal , Mark Willard Johnson , Sebastian Ahmed

IPC分类号： G06F9/345 , G06F9/32

CPC分类号： G06F9/3455 , G06F9/325

摘要： An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values.

5.

发明申请
Apparatus for Processor with Macro-Instruction and Associated Methods 有权

公开(公告)号：US20220413850A1

公开(公告)日：2022-12-29

申请号：US17361244

申请日：2021-06-28

申请人： Silicon Laboratories Inc.

发明人： Matthew Brandon Gately , Eric Jonathan Deal , Mark Willard Johnson , Daniel Thomas Riedler

IPC分类号： G06F9/30 , G06F9/38 , G06F9/52

摘要： An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.