公开(公告)号：US20220414051A1

公开(公告)日：2022-12-29

申请号：US17361257

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Daniel Thomas Riedler

IPC: G06F15/80 ,  G06F13/28 ,  G06F9/30

Abstract: An apparatus includes an array processor to process array data in response to information contained in a packet, wherein the packet comprises a set of fields specifying configuration information for processing the array.

公开(公告)号：US20240419448A1

公开(公告)日：2024-12-19

申请号：US18816208

申请日：2024-08-27

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Mark Willard Johnson ,  Sebastian Ahmed

IPC: G06F9/345 ,  G06F9/32

Abstract: An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values. A method for processing array data includes executing at least one loop by at least one corresponding loop controller of a plurality of loop controllers in an array processor. Each loop of the at least one loop is executed according to a corresponding begin flag and a corresponding end flag. The method may include generating an instruction stream by decoding a loop control field of a corresponding macro-instruction. The method may include configuring the corresponding begin flag and the corresponding end flag according to a corresponding begin flag field in the instruction stream and a corresponding end flag field in the instruction stream.

公开(公告)号：US12086597B2

公开(公告)日：2024-09-10

申请号：US17361250

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Mark Willard Johnson

IPC: G06F9/32 ,  G06F9/345

CPC classification number: G06F9/325 ,  G06F9/3455

Abstract: An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.

公开(公告)号：US12153921B2

公开(公告)日：2024-11-26

申请号：US17361244

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Mark Willard Johnson ,  Daniel Thomas Riedler

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.

公开(公告)号：US12153542B2

公开(公告)日：2024-11-26

申请号：US17361257

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Daniel Thomas Riedler

IPC: G06F9/30 ,  G06F13/28 ,  G06F15/80

Abstract: An apparatus includes an array processor to process array data in response to information contained in a packet, wherein the packet comprises a set of fields specifying configuration information for processing the array.

公开(公告)号：US20220414050A1

公开(公告)日：2022-12-29

申请号：US17361250

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Mark Willard Johnson

IPC: G06F15/173 ,  G06F9/38

Abstract: An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.

公开(公告)号：US20220414049A1

公开(公告)日：2022-12-29

申请号：US17361240

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Mark Willard Johnson ,  Sebastian Ahmed

IPC: G06F15/173 ,  G06F9/38

Abstract: An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values.

公开(公告)号：US12079630B2

公开(公告)日：2024-09-03

申请号：US17361240

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Mark Willard Johnson ,  Sebastian Ahmed

IPC: G06F9/345 ,  G06F9/32

CPC classification number: G06F9/3455 ,  G06F9/325

Abstract: An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values.

公开(公告)号：US20220413850A1

公开(公告)日：2022-12-29

申请号：US17361244

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Mark Willard Johnson ,  Daniel Thomas Riedler

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

Abstract: An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.