Invention Grant
- Patent Title: Method and apparatus for convolutional computation based on floating gate NVM array
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Application No.: US17373935Application Date: 2021-07-13
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Publication No.: US12174909B2Publication Date: 2024-12-24
- Inventor: Francesco La Rosa , Antonino Conte
- Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Rousset) SAS
- Applicant Address: IT Agrate Brianza; FR Rousset
- Assignee: STMicroelectronics S.r.l.,STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics S.r.l.,STMicroelectronics (Rousset) SAS
- Current Assignee Address: IT Agrate Brianza; FR Rousset
- Agency: Slater Matsil, LLP
- Priority: FR2008286 20200805
- Main IPC: G06F17/15
- IPC: G06F17/15 ; G11C16/04 ; G11C16/10 ; G11C16/26 ; G11C16/30 ; G11C16/32 ; G06N3/02 ; H03K19/20

Abstract:
In an embodiment a method programming floating gate transistors belonging to non-volatile memory cells to multilevel threshold voltages respectively corresponding to the weight factors, performing a sensing operation of the programmed floating gate transistors with a control signal adapted to make the corresponding memory cells become conductive at an instant determined by a respective programmed threshold voltage, performing the convolutional computation by using the input values during an elapsed time for each memory cell to become conductive and outputting output values resulting from the convolutional computation.
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