In certain aspects, a memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. The peripheral circuit includes frequency dividers and a clock path coupled to the frequency dividers. Each of the frequency dividers is configured to receive a clock signal and generate a clock return signal. The clock return signal corresponds to the clock signal. A period of the clock return signal is greater than the period of the clock signal. The clock path is configured to merge the clock return signals.