Invention Grant
- Patent Title: Bit error management in memory devices
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Application No.: US18049121Application Date: 2022-10-24
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Publication No.: US12189949B2Publication Date: 2025-01-07
- Inventor: Jeremy Binfet , Tommaso Vali , Walter Di Francesco , Luigi Pilolli , Angelo Covello , Andrea D'Alessandro , Agostino Macerola , Cristina Lattaro , Claudia Ciaschi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Harrity & Harrity, LLP
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.
Public/Granted literature
- US20230393739A1 BIT ERROR MANAGEMENT IN MEMORY DEVICES Public/Granted day:2023-12-07
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