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公开(公告)号：US12189949B2
公开(公告)日：2025-01-07
申请号：US18049121
申请日：2022-10-24
Applicant: Micron Technology, Inc.
Inventor： Jeremy Binfet , Tommaso Vali , Walter Di Francesco , Luigi Pilolli , Angelo Covello , Andrea D'Alessandro , Agostino Macerola , Cristina Lattaro , Claudia Ciaschi
IPC: G06F3/06
Abstract: In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.
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公开(公告)号：US11823743B2
公开(公告)日：2023-11-21
申请号：US17747516
申请日：2022-05-18
Applicant: Micron Technology, Inc.
Inventor： Shannon Marissa Hansen , Fulvio Rori , Andrea D'Alessandro , Jason Lee Nevill , Chiara Cerafogli
CPC classification number: G11C16/20 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/24 , G11C16/26 , H10B41/27 , H10B43/27
Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.
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公开(公告)号：US11776633B2
公开(公告)日：2023-10-03
申请号：US17120337
申请日：2020-12-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Ugo Russo , Violante Moschiano , William C. Filipiak , Andrea D'Alessandro
IPC: G11C8/00 , G11C16/26 , G11C16/10 , G11C16/34 , G11C16/04 , G11C5/14 , G11C11/4074 , G11C7/04 , G11C11/56
CPC classification number: G11C16/26 , G11C5/145 , G11C5/147 , G11C7/04 , G11C11/4074 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459
Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.
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公开(公告)号：US11170848B2
公开(公告)日：2021-11-09
申请号：US16791860
申请日：2020-02-14
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Andrea D'Alessandro , Andrea Giovanni Xotta
Abstract: The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.
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公开(公告)号：US20200066350A1
公开(公告)日：2020-02-27
申请号：US16655826
申请日：2019-10-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC: G11C16/12 , G11C16/34 , G11C11/4074 , G11C5/06 , G11C16/04
Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
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Patent Agency Ranking
公开(公告)号：US09165664B2
公开(公告)日：2015-10-20
申请号：US13935625
申请日：2013-07-05
Applicant: Micron Technology, Inc.
Inventor： Andrea D'Alessandro , Violante Moschiano
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/24
Abstract: Methods and apparatus for sensing operations in memory devices are disclosed. In at least one embodiment, a sensing operation to determine negative threshold voltages in memory cells by an elevated source potential applied to a string of memory cells and an elevated data line potential applied to the string of memory cells is disclosed. A ramped sense potential is incorporated into the sense operation according to at least one embodiment. A sense circuit diode allows a sense potential to fall below a data line potential during a sensing operation according to another embodiment.
Abstract translation: 公开了用于存储器件中的感测操作的方法和装置。 在至少一个实施例中，公开了一种通过施加到一串存储器单元的升高的源极电位和施加到存储器单元串的升高的数据线电位来确定存储器单元中的负阈值电压的感测操作。 根据至少一个实施例，将倾斜的感测电位并入到感测操作中。 根据另一实施例，感测电路二极管允许感测电位在感测操作期间降至数据线电位以下。
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公开(公告)号：US11721396B2
公开(公告)日：2023-08-08
申请号：US17012442
申请日：2020-09-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC: G11C16/12 , G11C11/4074 , G11C16/04 , G11C16/34 , G11C5/06
CPC classification number: G11C16/12 , G11C5/063 , G11C11/4074 , G11C16/0483 , G11C16/3427
Abstract: Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.
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公开(公告)号：US11309039B2
公开(公告)日：2022-04-19
申请号：US17202398
申请日：2021-03-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC: G11C16/34 , G11C16/26 , G11C8/08 , G11C11/413 , G11C5/06
Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.
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公开(公告)号：US10950316B2
公开(公告)日：2021-03-16
申请号：US16990137
申请日：2020-08-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC: G11C16/26 , G11C16/34 , G11C5/06 , G11C11/413 , G11C8/08
Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.
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公开(公告)号：US20200372961A1
公开(公告)日：2020-11-26
申请号：US16990137
申请日：2020-08-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC: G11C16/34 , G11C16/26 , G11C8/08 , G11C11/413 , G11C5/06
Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.
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