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公开(公告)号：US20230305616A1
公开(公告)日：2023-09-28
申请号：US18123399
申请日：2023-03-20
发明人： Luca Nubile , Walter Di Francesco , Luigi Pilolli
IPC分类号： G06F1/3225 , G06F1/10
CPC分类号： G06F1/3225 , G06F1/10
摘要： A memory device includes memory dies, a first memory die of the memory dies including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations including receiving a token from another memory die, in response to receiving the token, determining whether to reserve a data window during a token circulation time period having a first size determined based on a common clock signal shared among the memory dies and, in response to determining to reserve the data window, causing the data window to be reserved. The data window has a second size different from the first size determined based on the common clock signal. The operations further include causing a data frame to be generated within the data window. The data frame has a third size determined from the second size and includes current consumption information for the memory device.
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公开(公告)号：US20230134281A1
公开(公告)日：2023-05-04
申请号：US17976423
申请日：2022-10-28
发明人： Leo Raimondo , Federica Paolini , Umberto Siciliani , Violante Moschiano , Gianfranco Valeri , Davide Esposito , Walter Di Francesco
摘要： A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.
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公开(公告)号：US11636908B2
公开(公告)日：2023-04-25
申请号：US17485087
申请日：2021-09-24
发明人： Violante Moschiano , Walter Di Francesco , Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Jeffrey Scott McNeil, Jr.
摘要： A memory device to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages that are separated from each other by a first voltage interval. An estimate of a read level of the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages that are separated from each other by a second voltage interval that is smaller than the first voltage interval. An optimized read voltage for the read level is computed from the second signal and noise characteristics.
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公开(公告)号：US20230027820A1
公开(公告)日：2023-01-26
申请号：US17585165
申请日：2022-01-26
摘要： A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.
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公开(公告)号：US20220130482A1
公开(公告)日：2022-04-28
申请号：US17485087
申请日：2021-09-24
发明人： Violante Moschiano , Walter Di Francesco , Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Jeffrey Scott McNeil, JR.
摘要： A memory device to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages that are separated from each other by a first voltage interval. An estimate of a read level of the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages that are separated from each other by a second voltage interval that is smaller than the first voltage interval. An optimized read voltage for the read level is computed from the second signal and noise characteristics.
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公开(公告)号：US11120885B2
公开(公告)日：2021-09-14
申请号：US17100582
申请日：2020-11-20
发明人： Michael G. Miller , Kishore Kumar Muchherla , Harish R. Singidi , Walter Di Francesco , Renato C. Padilla , Gary F. Besinga , Violante Moschiano
摘要： An indication of an initialization of power to a memory device is received. Responsive to receiving the indication of the initialization of power to the memory device, whether a status indicator associated with a written page of the memory device can be read is determined. Responsive to determining that the status indicator cannot be read, a programming of data to the memory device did not complete based on a prior loss of power to the memory device is determined.
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公开(公告)号：US20210103389A1
公开(公告)日：2021-04-08
申请号：US17123472
申请日：2020-12-16
发明人： Sivagnanam Parthasarathy , Terry M. Grunzke , Lucia Botticchio , Walter Di Francesco , Vamshi K. Indavarapu , Gianfranco Valeri , Renato C. Padilla , Ali Mohammadzadeh , Jung Sheng Hoei , Luca De Santis
IPC分类号： G06F3/06 , G06F12/02 , G06F12/1009
摘要： The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.
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公开(公告)号：US12007912B2
公开(公告)日：2024-06-11
申请号：US17814395
申请日：2022-07-22
CPC分类号： G06F12/1466 , G11C16/22 , G06F2212/1052 , G11C16/0483
摘要： In some implementations, a memory device may resolve a set of latches of a NAND page buffer to a set of initialized values. The memory device may obtain a NAND page buffer initialized data set from the set of initialized values of the set of latches. The memory device may generate a security key using the NAND page buffer initialized data set.
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公开(公告)号：US12001336B2
公开(公告)日：2024-06-04
申请号：US17585165
申请日：2022-01-26
CPC分类号： G06F12/0842 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/30 , G11C16/3459 , G06F2212/1024
摘要： A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.
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公开(公告)号：US20240061592A1
公开(公告)日：2024-02-22
申请号：US18231338
申请日：2023-08-08
发明人： Chulbum Kim , Jonathan S. Parry , Luca Nubile , Ali Mohammadzadeh , Biagio Iorio , Liang Yu , Jeremy Binfet , Walter Di Francesco , Daniel J. Hubbard , Luigi Pilolli
IPC分类号： G06F3/06 , G06F1/3234
CPC分类号： G06F3/0625 , G06F3/0659 , G06F3/0679 , G06F1/3275
摘要： A method includes receiving a request to perform a memory access operation, wherein the memory access operation includes a set of sub-operations, selecting a current quantization data structure from a plurality of current quantization data structures, wherein each current quantization data structure of the plurality of current quantization data structures maintains, for each sub-operation of the set of sub-operations, a respective current quantization value reflecting an amount of current that is consumed by the respective sub-operation based on a set of peak power management (PPM) operation parameters, and causing the memory access operation to be performed using PPM based on the current quantization data structure.
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